src/mainboard/tyan/s4880/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4 default CONFIG_ROM_PAYLOAD = 1
   5
   6 arch i386 end
   7
   8
   9 ##
  10 ## Build the objects we have code for in this directory.
  11 ##
  12
  13 driver mainboard.o
  14 if CONFIG_HAVE_MP_TABLE object mptable.o end
  15 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
  16
  17         if CONFIG_USE_INIT
  18
  19                 makerule ./auto.o
  20                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  21                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  22                 end
  23
  24         else
  25
  26                 makerule ./auto.inc
  27                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  28                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  29                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  30                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  31                         end
  32         end
  33
  34 ##
  35 ## Build our 16 bit and 32 bit coreboot entry code
  36 ##
  37 if CONFIG_USE_FALLBACK_IMAGE
  38         mainboardinit cpu/x86/16bit/entry16.inc
  39         ldscript /cpu/x86/16bit/entry16.lds
  40 end
  41
  42 mainboardinit cpu/x86/32bit/entry32.inc
  43
  44         if CONFIG_USE_INIT
  45                 ldscript /cpu/x86/32bit/entry32.lds
  46         end
  47
  48         if CONFIG_USE_INIT
  49                 ldscript /cpu/amd/car/cache_as_ram.lds
  50         end
  51
  52 ##
  53 ## Build our reset vector (This is where coreboot is entered)
  54 ##
  55 if CONFIG_USE_FALLBACK_IMAGE
  56         mainboardinit cpu/x86/16bit/reset16.inc
  57         ldscript /cpu/x86/16bit/reset16.lds
  58 else
  59         mainboardinit cpu/x86/32bit/reset32.inc
  60         ldscript /cpu/x86/32bit/reset32.lds
  61 end
  62
  63 ##
  64 ## Include an id string (For safe flashing)
  65 ##
  66 mainboardinit arch/i386/lib/id.inc
  67 ldscript /arch/i386/lib/id.lds
  68
  69         ##
  70         ## Setup Cache-As-Ram
  71         ##
  72         mainboardinit cpu/amd/car/cache_as_ram.inc
  73
  74 ###
  75 ### This is the early phase of coreboot startup
  76 ### Things are delicate and we test to see if we should
  77 ### failover to another image.
  78 ###
  79 if CONFIG_USE_FALLBACK_IMAGE
  80                 ldscript /arch/i386/lib/failover.lds
  81 end
  82
  83 ##
  84 ## Setup RAM
  85 ##
  86         if CONFIG_USE_INIT
  87                 initobject auto.o
  88         else
  89                 mainboardinit ./auto.inc
  90         end
  91
  92 ##
  93 ## Include the secondary Configuration files
  94 ##
  95 config chip.h
  96
  97 # sample config for tyan/s4880
  98 chip northbridge/amd/amdk8/root_complex
  99         device apic_cluster 0 on
 100                 chip cpu/amd/socket_940
 101                         device apic 0 on end
 102                 end
 103         end
 104
 105         device pci_domain 0 on
 106                 chip northbridge/amd/amdk8
 107                         device pci 18.0 on end # LDT0
 108                         device pci 18.0 on end # LDT1
 109                         device pci 18.0 on #  northbridge
 110                                 #  devices on link 2, link 2 == LDT 2
 111                                 chip southbridge/amd/amd8131
 112                                         # the on/off keyword is mandatory
 113                                         device pci 0.0 on
 114 #                                                chip drivers/lsi/53c1030
 115 #                                                        device pci 4.0 on end
 116 #                                                        device pci 4.1 on end
 117 #                                                        register "fw_address" = "0xfff8c000"
 118 #                                                end
 119                                                 chip drivers/pci/onboard
 120                                                         device pci 9.0 on end
 121                                                         device pci 9.1 on end
 122                                                 end
 123                                         end
 124                                         device pci 0.1 on end
 125                                         device pci 1.0 on end
 126                                         device pci 1.1 on end
 127                                 end
 128                                 chip southbridge/amd/amd8111
 129                                         # this "device pci 0.0" is the parent the next one
 130                                         # PCI bridge
 131                                         device pci 0.0 on
 132                                                 device pci 0.0 on end
 133                                                 device pci 0.1 on end
 134                                                 device pci 0.2 off end
 135                                                 device pci 1.0 off end
 136                                                 chip drivers/pci/onboard
 137                                                         device pci 6.0 on end
 138                                                         register "rom_address" = "0xfff80000"
 139                                                 end
 140                                         end
 141                                         device pci 1.0 on
 142                                                 chip superio/winbond/w83627hf
 143                                                         device pnp 2e.0 on #  Floppy
 144                                                                 io 0x60 = 0x3f0
 145                                                                 irq 0x70 = 6
 146                                                                 drq 0x74 = 2
 147                                                         end
 148                                                         device pnp 2e.1 off #  Parallel Port
 149                                                                 io 0x60 = 0x378
 150                                                                 irq 0x70 = 7
 151                                                         end
 152                                                         device pnp 2e.2 on #  Com1
 153                                                                 io 0x60 = 0x3f8
 154                                                                 irq 0x70 = 4
 155                                                         end
 156                                                         device pnp 2e.3 off #  Com2
 157                                                                 io 0x60 = 0x2f8
 158                                                                 irq 0x70 = 3
 159                                                         end
 160                                                         device pnp 2e.5 on #  Keyboard
 161                                                                 io 0x60 = 0x60
 162                                                                 io 0x62 = 0x64
 163                                                                 irq 0x70 = 1
 164                                                                 irq 0x72 = 12
 165                                                         end
 166                                                         device pnp 2e.6 off #  CIR
 167                                                                 io 0x60 = 0x100
 168                                                         end
 169                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 170                                                                 io 0x60 = 0x220
 171                                                                 io 0x62 = 0x300
 172                                                                 irq 0x70 = 9
 173                                                         end
 174                                                         device pnp 2e.8 off end #  GPIO2
 175                                                         device pnp 2e.9 off end #  GPIO3
 176                                                         device pnp 2e.a off end #  ACPI
 177                                                         device pnp 2e.b on #  HW Monitor
 178                                                                 io 0x60 = 0x290
 179                                                                 irq 0x70 = 5
 180                                                         end
 181                                                 end
 182                                         end
 183                                         device pci 1.1 on end
 184                                         device pci 1.2 on end
 185                                         device pci 1.3 on end
 186                                         device pci 1.5 off end
 187                                         device pci 1.6 off end
 188                                         register "ide0_enable" = "1"
 189                                         register "ide1_enable" = "1"
 190                                 end
 191                         end #  device pci 18.0
 192
 193                         device pci 18.1 on end
 194                         device pci 18.2 on end
 195                         device pci 18.3 on end
 196                 end
 197
 198         end #pci_domain
 199 end
 200