src/mainboard/tyan/s2891/romstage.c

   1 //used by raminit
   2 #define QRANK_DIMM_SUPPORT 1
   3
   4 #if CONFIG_LOGICAL_CPUS==1
   5 #define SET_NB_CFG_54 1
   6 #endif
   7
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <device/pci_def.h>
  11 #include <arch/io.h>
  12 #include <device/pnp_def.h>
  13 #include <arch/romcc_io.h>
  14 #include <cpu/x86/lapic.h>
  15 #include "option_table.h"
  16 #include "pc80/mc146818rtc_early.c"
  17 #include <console/console.h>
  18 #include "lib/ramtest.c"
  19
  20 #include <cpu/amd/model_fxx_rev.h>
  21
  22 #include "northbridge/amd/amdk8/incoherent_ht.c"
  23 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  24 #include "northbridge/amd/amdk8/raminit.h"
  25 #include "cpu/amd/model_fxx/apic_timer.c"
  26 #include "lib/delay.c"
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "cpu/x86/mtrr/earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  38
  39 static void memreset_setup(void)
  40 {
  41 }
  42
  43 static void memreset(int controllers, const struct mem_controller *ctrl)
  44 {
  45 }
  46
  47 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  48 {
  49         /* nothing to do */
  50 }
  51
  52 static inline int spd_read_byte(unsigned device, unsigned address)
  53 {
  54         return smbus_read_byte(device, address);
  55 }
  56
  57 #include "northbridge/amd/amdk8/raminit.c"
  58 #include "northbridge/amd/amdk8/coherent_ht.c"
  59 #include "lib/generic_sdram.c"
  60
  61  /* tyan does not want the default */
  62 #include "resourcemap.c"
  63
  64 #include "cpu/amd/dualcore/dualcore.c"
  65
  66 #define CK804_NUM 1
  67 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  68 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  69
  70
  71
  72 #include "cpu/amd/car/post_cache_as_ram.c"
  73
  74 #include "cpu/amd/model_fxx/init_cpus.c"
  75
  76 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  77 #include "northbridge/amd/amdk8/early_ht.c"
  78
  79 static void sio_setup(void)
  80 {
  81         uint32_t dword;
  82         uint8_t byte;
  83
  84         /* subject decoding*/
  85         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  86         byte |= 0x20;
  87         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  88
  89         /* LPC Positive Decode 0 */
  90         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  91         /* Serial 0, Serial 1 */
  92         dword |= (1<<0) | (1<<1);
  93         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  94
  95 #if 1
  96         /* s2891 has onboard LPC port 80 */
  97         /*Hope I can enable port 80 here
  98         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  99         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
 100         dword |= (1<<16);
 101         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 102 #endif
 103 }
 104
 105 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 106 {
 107         static const uint16_t spd_addr [] = {
 108                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 109                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 110 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 111                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 112                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 113 #endif
 114         };
 115
 116         int needs_reset;
 117         unsigned bsp_apicid = 0;
 118
 119         struct mem_controller ctrl[8];
 120         unsigned nodes;
 121
 122         if (!cpu_init_detectedx && boot_cpu()) {
 123                 /* Nothing special needs to be done to find bus 0 */
 124                 /* Allow the HT devices to be found */
 125
 126                 enumerate_ht_chain();
 127
 128                 sio_setup();
 129
 130                 /* Setup the ck804 */
 131                 ck804_enable_rom();
 132         }
 133
 134         if (bist == 0) {
 135                 bsp_apicid = init_cpus(cpu_init_detectedx);
 136         }
 137
 138 //      post_code(0x32);
 139
 140         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 141         uart_init();
 142         console_init();
 143
 144         /* Halt if there was a built in self test failure */
 145         report_bist_failure(bist);
 146
 147         setup_s2891_resource_map();
 148 #if 0
 149         dump_pci_device(PCI_DEV(0, 0x18, 0));
 150         dump_pci_device(PCI_DEV(0, 0x19, 0));
 151 #endif
 152
 153         needs_reset = setup_coherent_ht_domain();
 154
 155         wait_all_core0_started();
 156 #if CONFIG_LOGICAL_CPUS==1
 157         // It is said that we should start core1 after all core0 launched
 158         start_other_cores();
 159         wait_all_other_cores_started(bsp_apicid);
 160 #endif
 161
 162         needs_reset |= ht_setup_chains_x();
 163
 164         needs_reset |= ck804_early_setup_x();
 165
 166         if (needs_reset) {
 167                 printk(BIOS_INFO, "ht reset -\n");
 168                 soft_reset();
 169         }
 170
 171         allow_all_aps_stop(bsp_apicid);
 172
 173         nodes = get_nodes();
 174         //It's the time to set ctrl now;
 175         fill_mem_ctrl(nodes, ctrl, spd_addr);
 176
 177         enable_smbus();
 178 #if 0
 179         dump_spd_registers(&cpu[0]);
 180 #endif
 181 #if 0
 182         dump_smbus_registers();
 183 #endif
 184
 185         memreset_setup();
 186         sdram_initialize(nodes, ctrl);
 187
 188 #if 0
 189         print_pci_devices();
 190 #endif
 191
 192 #if 0
 193         dump_pci_devices();
 194 #endif
 195
 196         post_cache_as_ram();
 197 }
 198