src/mainboard/tyan/s2885/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16
  17 #if 0
  18 static void post_code(uint8_t value) {
  19 #if 1
  20         int i;
  21         for(i=0;i<0x80000;i++) {
  22                 outb(value, 0x80);
  23         }
  24 #endif
  25 }
  26 #endif
  27
  28 #include <cpu/amd/model_fxx_rev.h>
  29
  30 #include "northbridge/amd/amdk8/incoherent_ht.c"
  31 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  32 #include "northbridge/amd/amdk8/raminit.h"
  33 #include "cpu/amd/model_fxx/apic_timer.c"
  34 #include "lib/delay.c"
  35
  36 #include "cpu/x86/lapic/boot_cpu.c"
  37 #include "northbridge/amd/amdk8/reset_test.c"
  38 #include "northbridge/amd/amdk8/debug.c"
  39 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  40
  41 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  42 #include "cpu/x86/bist.h"
  43
  44 #include "northbridge/amd/amdk8/setup_resource_map.c"
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  47
  48 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  49
  50 static void memreset_setup(void)
  51 {
  52    if (is_cpu_pre_c0()) {
  53         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  54    }
  55    else {
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  57    }
  58         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63    if (is_cpu_pre_c0()) {
  64         udelay(800);
  65         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  66         udelay(90);
  67    }
  68 }
  69
  70 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  71 {
  72         /* nothing to do */
  73 }
  74
  75 static inline int spd_read_byte(unsigned device, unsigned address)
  76 {
  77         return smbus_read_byte(device, address);
  78 }
  79
  80 #define QRANK_DIMM_SUPPORT 1
  81
  82 #include "northbridge/amd/amdk8/raminit.c"
  83 #include "northbridge/amd/amdk8/coherent_ht.c"
  84 #include "sdram/generic_sdram.c"
  85
  86  /* tyan does not want the default */
  87 #include "resourcemap.c"
  88
  89 #if CONFIG_LOGICAL_CPUS==1
  90 #define SET_NB_CFG_54 1
  91 #endif
  92 #include "cpu/amd/dualcore/dualcore.c"
  93
  94
  95 #include "cpu/amd/car/copy_and_run.c"
  96
  97 #include "cpu/amd/car/post_cache_as_ram.c"
  98
  99 #include "cpu/amd/model_fxx/init_cpus.c"
 100
 101
 102 #if CONFIG_USE_FALLBACK_IMAGE == 1
 103
 104 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 105 #include "northbridge/amd/amdk8/early_ht.c"
 106
 107 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 108 {
 109         unsigned last_boot_normal_x = last_boot_normal();
 110
 111         /* Is this a cpu only reset? or Is this a secondary cpu? */
 112         if ((cpu_init_detectedx) || (!boot_cpu())) {
 113                 if (last_boot_normal_x) {
 114                         goto normal_image;
 115                 } else {
 116                         goto fallback_image;
 117                 }
 118         }
 119
 120         /* Nothing special needs to be done to find bus 0 */
 121         /* Allow the HT devices to be found */
 122
 123         enumerate_ht_chain();
 124
 125         /* Setup the ck804 */
 126         amd8111_enable_rom();
 127
 128         /* Is this a deliberate reset by the bios */
 129 //        post_code(0x22);
 130         if (bios_reset_detected() && last_boot_normal_x) {
 131                 goto normal_image;
 132         }
 133         /* This is the primary cpu how should I boot? */
 134         else if (do_normal_boot()) {
 135                 goto normal_image;
 136         }
 137         else {
 138                 goto fallback_image;
 139         }
 140  normal_image:
 141 //        post_code(0x23);
 142         __asm__ volatile ("jmp __normal_image"
 143                 : /* outputs */
 144                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 145                 );
 146
 147  fallback_image:
 148 //        post_code(0x25);
 149         ;
 150 }
 151 #endif
 152
 153 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 154
 155 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 156 {
 157
 158 #if CONFIG_USE_FALLBACK_IMAGE == 1
 159         failover_process(bist, cpu_init_detectedx);
 160 #endif
 161         real_main(bist, cpu_init_detectedx);
 162
 163 }
 164
 165 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 166 {
 167         static const uint16_t spd_addr [] = {
 168                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 169                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 170 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 171                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 172                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 173 #endif
 174         };
 175
 176         int needs_reset;
 177         unsigned bsp_apicid = 0;
 178
 179         struct mem_controller ctrl[8];
 180         unsigned nodes;
 181
 182         if (bist == 0) {
 183                 bsp_apicid = init_cpus(cpu_init_detectedx);
 184         }
 185
 186 //      post_code(0x32);
 187
 188         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 189         uart_init();
 190         console_init();
 191
 192 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 193
 194         /* Halt if there was a built in self test failure */
 195         report_bist_failure(bist);
 196
 197         setup_s2885_resource_map();
 198 #if 0
 199         dump_pci_device(PCI_DEV(0, 0x18, 0));
 200         dump_pci_device(PCI_DEV(0, 0x19, 0));
 201 #endif
 202
 203         needs_reset = setup_coherent_ht_domain();
 204
 205         wait_all_core0_started();
 206 #if CONFIG_LOGICAL_CPUS==1
 207         // It is said that we should start core1 after all core0 launched
 208         start_other_cores();
 209         wait_all_other_cores_started(bsp_apicid);
 210 #endif
 211
 212         needs_reset |= ht_setup_chains_x();
 213
 214         if (needs_reset) {
 215                 print_info("ht reset -\r\n");
 216                 soft_reset();
 217         }
 218
 219
 220         allow_all_aps_stop(bsp_apicid);
 221
 222         nodes = get_nodes();
 223         //It's the time to set ctrl now;
 224         fill_mem_ctrl(nodes, ctrl, spd_addr);
 225
 226         enable_smbus();
 227
 228         memreset_setup();
 229         sdram_initialize(nodes, ctrl);
 230
 231 #if 0
 232         dump_pci_devices();
 233 #endif
 234
 235         post_cache_as_ram();
 236
 237 }