4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
34 uses MAINBOARD_PART_NUMBER
37 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
44 uses DEFAULT_CONSOLE_LOGLEVEL
45 uses MAXIMUM_CONSOLE_LOGLEVEL
46 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses HW_MEM_HOLE_SIZEK
63 uses CONFIG_USE_PRINTK_IN_CAR
70 ## ROM_SIZE is the size of boot ROM that this board will use.
72 default ROM_SIZE=524288
75 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
77 #default FALLBACK_SIZE=131072
79 default FALLBACK_SIZE=0x40000
82 ## Build code for the fallback boot
84 default HAVE_FALLBACK_BOOT=1
87 ## Build code to reset the motherboard from coreboot
89 default HAVE_HARD_RESET=1
92 ## Build code to export a programmable irq routing table
94 default HAVE_PIRQ_TABLE=1
95 default IRQ_SLOT_COUNT=15
98 ## Build code to export an x86 MP table
99 ## Useful for specifying IRQ routing values
101 default HAVE_MP_TABLE=1
104 ## Build code to export a CMOS option table
106 default HAVE_OPTION_TABLE=1
109 ## Move the default coreboot cmos range off of AMD RTC registers
111 default LB_CKS_RANGE_START=49
112 default LB_CKS_RANGE_END=122
113 default LB_CKS_LOC=123
116 ## Build code for SMP support
117 ## Only worry about 2 micro processors
120 default CONFIG_MAX_CPUS=4
121 default CONFIG_MAX_PHYSICAL_CPUS=2
122 default CONFIG_LOGICAL_CPUS=1
125 default HW_MEM_HOLE_SIZEK=0x100000
128 default CONFIG_CONSOLE_VGA=1
129 default CONFIG_PCI_ROM_RUN=1
133 ## enable CACHE_AS_RAM specifics
135 default USE_DCACHE_RAM=1
136 default DCACHE_RAM_BASE=0xcf000
137 default DCACHE_RAM_SIZE=0x1000
138 default CONFIG_USE_INIT=0
141 ## Build code to setup a generic IOAPIC
143 default CONFIG_IOAPIC=1
146 ## Clean up the motherboard id strings
148 default MAINBOARD_PART_NUMBER="S2882"
149 default MAINBOARD_VENDOR="Tyan"
150 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
151 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
154 ### coreboot layout values
157 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
158 default ROM_IMAGE_SIZE = 65536
161 ## Use a small 8K stack
163 default STACK_SIZE=0x2000
166 ## Use a small 16K heap
168 default HEAP_SIZE=0x4000
171 ## Only use the option table in a normal image
173 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
176 ## Coreboot C code runs at this location in RAM
178 default _RAMBASE=0x00004000
181 ## Load the payload from the ROM
183 default CONFIG_ROM_PAYLOAD = 1
186 ### Defaults of options that you may want to override in the target config file
190 ## The default compiler
192 default CC="$(CROSS_COMPILE)gcc -m32"
196 ## Disable the gdb stub by default
198 default CONFIG_GDB_STUB=0
200 default CONFIG_USE_PRINTK_IN_CAR=1
203 ## The Serial Console
206 # To Enable the Serial Console
207 default CONFIG_CONSOLE_SERIAL8250=1
209 ## Select the serial console baud rate
210 default TTYS0_BAUD=115200
211 #default TTYS0_BAUD=57600
212 #default TTYS0_BAUD=38400
213 #default TTYS0_BAUD=19200
214 #default TTYS0_BAUD=9600
215 #default TTYS0_BAUD=4800
216 #default TTYS0_BAUD=2400
217 #default TTYS0_BAUD=1200
219 # Select the serial console base port
220 default TTYS0_BASE=0x3f8
222 # Select the serial protocol
223 # This defaults to 8 data bits, 1 stop bit, and no parity
224 default TTYS0_LCS=0x3
227 ### Select the coreboot loglevel
229 ## EMERG 1 system is unusable
230 ## ALERT 2 action must be taken immediately
231 ## CRIT 3 critical conditions
232 ## ERR 4 error conditions
233 ## WARNING 5 warning conditions
234 ## NOTICE 6 normal but significant condition
235 ## INFO 7 informational
236 ## DEBUG 8 debug-level messages
237 ## SPEW 9 Way too many details
239 ## Request this level of debugging output
240 default DEFAULT_CONSOLE_LOGLEVEL=8
241 ## At a maximum only compile in this level of debugging
242 default MAXIMUM_CONSOLE_LOGLEVEL=8
245 ## Select power on after power fail setting
246 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
253 default CONFIG_CBFS=0