1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
8 ## Build the objects we have code for in this directory.
15 if CONFIG_HAVE_MP_TABLE object mptable.o end
16 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
21 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
22 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
28 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
29 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
30 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
31 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
36 ## Build our 16 bit and 32 bit coreboot entry code
38 if CONFIG_USE_FALLBACK_IMAGE
39 mainboardinit cpu/x86/16bit/entry16.inc
40 ldscript /cpu/x86/16bit/entry16.lds
43 mainboardinit cpu/x86/32bit/entry32.inc
46 ldscript /cpu/x86/32bit/entry32.lds
50 ldscript /cpu/amd/car/cache_as_ram.lds
54 ## Build our reset vector (This is where coreboot is entered)
56 if CONFIG_USE_FALLBACK_IMAGE
57 mainboardinit cpu/x86/16bit/reset16.inc
58 ldscript /cpu/x86/16bit/reset16.lds
60 mainboardinit cpu/x86/32bit/reset32.inc
61 ldscript /cpu/x86/32bit/reset32.lds
65 ## Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
73 mainboardinit cpu/amd/car/cache_as_ram.inc
76 ### This is the early phase of coreboot startup
77 ### Things are delicate and we test to see if we should
78 ### failover to another image.
80 if CONFIG_USE_FALLBACK_IMAGE
81 ldscript /arch/i386/lib/failover.lds
85 ### O.k. We aren't just an intermediary anymore!
94 mainboardinit ./auto.inc
98 ## Include the secondary Configuration files
102 # sample config for tyan/s2882
103 chip northbridge/amd/amdk8/root_complex
104 device apic_cluster 0 on
105 chip cpu/amd/socket_940
110 device pci_domain 0 on
111 chip northbridge/amd/amdk8
112 device pci 18.0 on # northbridge
113 # devices on link 0, link 0 == LDT 0
114 chip southbridge/amd/amd8131
115 # the on/off keyword is mandatory
117 chip drivers/pci/onboard
118 device pci 6.0 on end # adaptec
119 device pci 6.1 on end
121 chip drivers/pci/onboard
122 device pci 9.0 on end # broadcom 5704
123 device pci 9.1 on end
126 device pci 0.1 on end
127 device pci 1.0 on end
128 device pci 1.1 on end
130 chip southbridge/amd/amd8111
131 # this "device pci 0.0" is the parent the next one
134 device pci 0.0 on end
135 device pci 0.1 on end
136 device pci 0.2 off end
137 device pci 1.0 off end
138 chip drivers/pci/onboard
139 device pci 5.0 on end
141 # chip drivers/ati/ragexl
142 chip drivers/pci/onboard
143 device pci 6.0 on end
144 register "rom_address" = "0xfff00000"
146 chip drivers/pci/onboard
147 device pci 8.0 on end #intel 10/100
151 chip superio/winbond/w83627hf
152 device pnp 2e.0 on # Floppy
157 device pnp 2e.1 off # Parallel Port
161 device pnp 2e.2 on # Com1
165 device pnp 2e.3 off # Com2
169 device pnp 2e.5 on # Keyboard
175 device pnp 2e.6 off # CIR
178 device pnp 2e.7 off # GAME_MIDI_GIPO1
183 device pnp 2e.8 off end # GPIO2
184 device pnp 2e.9 off end # GPIO3
185 device pnp 2e.a off end # ACPI
186 device pnp 2e.b on # HW Monitor
192 device pci 1.1 on end
193 device pci 1.2 on end
194 device pci 1.3 on end
196 # chip drivers/generic/generic #dimm 0-0-0
197 # device i2c 50 on end
199 # chip drivers/generic/generic #dimm 0-0-1
200 # device i2c 51 on end
202 # chip drivers/generic/generic #dimm 0-1-0
203 # device i2c 52 on end
205 # chip drivers/generic/generic #dimm 0-1-1
206 # device i2c 53 on end
208 # chip drivers/generic/generic #dimm 1-0-0
209 # device i2c 54 on end
211 # chip drivers/generic/generic #dimm 1-0-1
212 # device i2c 55 on end
214 # chip drivers/generic/generic #dimm 1-1-0
215 # device i2c 56 on end
217 # chip drivers/generic/generic #dimm 1-1-1
218 # device i2c 57 on end
221 device pci 1.5 off end
222 device pci 1.6 off end
223 register "ide0_enable" = "1"
224 register "ide1_enable" = "1"
226 end # device pci 18.0
228 device pci 18.0 on end
229 device pci 18.0 on end
231 device pci 18.1 on end
232 device pci 18.2 on end
233 device pci 18.3 on end