src/mainboard/supermicro/x6dhe_g/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <device/pci.h>
   4 #include <string.h>
   5 #include <stdint.h>
   6
   7 void *smp_write_config_table(void *v)
   8 {
   9         static const char sig[4] = "PCMP";
  10         static const char oem[8] = "LNXI    ";
  11         static const char productid[12] = "X6DHE       ";
  12         struct mp_config_table *mc;
  13         unsigned char bus_num;
  14         unsigned char bus_isa;
  15         unsigned char bus_pxhd_1;
  16         unsigned char bus_pxhd_2;
  17         unsigned char bus_esb6300_1;
  18         unsigned char bus_esb6300_2;
  19
  20         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  21         memset(mc, 0, sizeof(*mc));
  22
  23         memcpy(mc->mpc_signature, sig, sizeof(sig));
  24         mc->mpc_length = sizeof(*mc); /* initially just the header */
  25         mc->mpc_spec = 0x04;
  26         mc->mpc_checksum = 0; /* not yet computed */
  27         memcpy(mc->mpc_oem, oem, sizeof(oem));
  28         memcpy(mc->mpc_productid, productid, sizeof(productid));
  29         mc->mpc_oemptr = 0;
  30         mc->mpc_oemsize = 0;
  31         mc->mpc_entry_count = 0; /* No entries yet... */
  32         mc->mpc_lapic = LAPIC_ADDR;
  33         mc->mpe_length = 0;
  34         mc->mpe_checksum = 0;
  35         mc->reserved = 0;
  36
  37         smp_write_processors(mc);
  38
  39         {
  40                 device_t dev;
  41
  42                 /* esb6300_2 */
  43                 dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
  44                 if (dev) {
  45                         bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  46                 }
  47                 else {
  48                         printk_debug("ERROR - could not find PCI 0:1c.0, using defaults\n");
  49
  50                         bus_esb6300_2 = 6;
  51                 }
  52                 /* esb6300_1 */
  53                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  54                 if (dev) {
  55                         bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  56                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  57                         bus_isa++;
  58                 }
  59                 else {
  60                         printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
  61
  62                         bus_esb6300_1 = 7;
  63                         bus_isa = 8;
  64                 }
  65                 /* pxhd-1 */
  66                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  67                 if (dev) {
  68                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  69
  70                 }
  71                 else {
  72                         printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n");
  73
  74                         bus_pxhd_1 = 2;
  75                 }
  76                 /* pxhd-2 */
  77                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  78                 if (dev) {
  79                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  80
  81                 }
  82                 else {
  83                         printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
  84
  85                         bus_pxhd_2 = 3;
  86                 }
  87         }
  88
  89         /* define bus and isa numbers */
  90         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
  91                 smp_write_bus(mc, bus_num, "PCI   ");
  92         }
  93         smp_write_bus(mc, bus_isa, "ISA   ");
  94
  95         /* IOAPIC handling */
  96
  97         smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
  98         smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
  99         {
 100                 struct resource *res;
 101                 device_t dev;
 102                 /* PXHd apic 4 */
 103                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
 104                 if (dev) {
 105                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 106                         if (res) {
 107                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
 108                         }
 109                 }
 110                 else {
 111                         printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
 112                         printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
 113                 }
 114                 /* PXHd apic 5 */
 115                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
 116                 if (dev) {
 117                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 118                         if (res) {
 119                                 smp_write_ioapic(mc, 0x05, 0x20, res->base);
 120                         }
 121                 }
 122                 else {
 123                         printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
 124                         printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
 125                 }
 126         }
 127
 128
 129         /* ISA backward compatibility interrupts  */
 130         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 131                 bus_isa, 0x00, 0x02, 0x00);
 132         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 133                 bus_isa, 0x01, 0x02, 0x01);
 134         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 135                 bus_isa, 0x00, 0x02, 0x02);
 136         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 137                 bus_isa, 0x03, 0x02, 0x03);
 138         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 139                 bus_isa, 0x04, 0x02, 0x04);
 140         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 141                 0x00, 0x74, 0x02, 0x10);
 142         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 143                 bus_isa, 0x06, 0x02, 0x06);
 144         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, // added
 145                 bus_isa, 0x07, 0x02, 0x07);
 146         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 147                 bus_isa, 0x08, 0x02, 0x08);
 148         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 149                 bus_isa, 0x09, 0x02, 0x09);
 150         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 151                 0x00, 0x77, 0x02, 0x17);
 152         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 153                 0x00, 0x75, 0x02, 0x13);
 154         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 155                 bus_isa, 0x0c, 0x02, 0x0c);
 156         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 157                 bus_isa, 0x0d, 0x02, 0x0d);
 158         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 159                 bus_isa, 0x0e, 0x02, 0x0e);
 160         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 161                 bus_isa, 0x0f, 0x02, 0x0f);
 162         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 163                 0x00, 0x7c, 0x02, 0x12);
 164         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 165                 0x00, 0x7d, 0x02, 0x11);
 166         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 167                 0x03, 0x08, 0x05, 0x00);
 168         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 169                 0x03, 0x08, 0x05, 0x04);
 170         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 171                 bus_esb6300_1, 0x04, 0x03, 0x00);
 172         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 173                 bus_esb6300_1, 0x08, 0x03, 0x01);
 174         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 175                 bus_esb6300_2, 0x04, 0x02, 0x10);
 176         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 177                 bus_esb6300_2, 0x08, 0x02, 0x14);
 178
 179         /* Standard local interrupt assignments */
 180         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 181                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 182         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 183                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 184
 185 #warning "FIXME verify I have the irqs handled for all of the risers"
 186
 187         /* Compute the checksums */
 188         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 189
 190         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 191         printk_debug("Wrote the mp table end at: %p - %p\n",
 192                 mc, smp_next_mpe_entry(mc));
 193         return smp_next_mpe_entry(mc);
 194 }
 195
 196 unsigned long write_smp_table(unsigned long addr)
 197 {
 198         void *v;
 199         v = smp_write_floating_table(addr);
 200         return (unsigned long)smp_write_config_table(v);
 201 }
 202