3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses CONFIG_LOGICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_STREAM
19 uses CONFIG_ROM_STREAM_START
27 uses LB_CKS_RANGE_START
31 uses MAINBOARD_PART_NUMBER
33 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
34 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
35 uses LINUXBIOS_EXTRA_VERSION
36 uses CONFIG_UDELAY_TSC
37 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
40 uses CONFIG_CONSOLE_SERIAL8250
44 uses DEFAULT_CONSOLE_LOGLEVEL
45 uses MAXIMUM_CONSOLE_LOGLEVEL
46 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_BTEXT
59 ## ROM_SIZE is the size of boot ROM that this board will use.
61 default ROM_SIZE=1048576
64 ## Build code for the fallback boot
66 default HAVE_FALLBACK_BOOT=1
69 ## Delay timer options
72 default CONFIG_UDELAY_TSC=1
73 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
76 ## Build code to reset the motherboard from linuxBIOS
78 default HAVE_HARD_RESET=1
81 ## Build code to export a programmable irq routing table
83 default HAVE_PIRQ_TABLE=1
84 default IRQ_SLOT_COUNT=16
87 ## Build code to export an x86 MP table
88 ## Useful for specifying IRQ routing values
90 default HAVE_MP_TABLE=1
93 ## Build code to export a CMOS option table
95 default HAVE_OPTION_TABLE=1
98 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
100 default LB_CKS_RANGE_START=49
101 default LB_CKS_RANGE_END=122
102 default LB_CKS_LOC=123
105 ## Build code for SMP support
106 ## Only worry about 2 micro processors
109 default CONFIG_MAX_CPUS=4
110 default CONFIG_LOGICAL_CPUS=0
113 ## Build code to setup a generic IOAPIC
115 default CONFIG_IOAPIC=1
118 ## Clean up the motherboard id strings
120 default MAINBOARD_PART_NUMBER="X6DAI"
121 default MAINBOARD_VENDOR= "Supermicro"
122 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
123 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
126 ### LinuxBIOS layout values
129 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
130 default ROM_IMAGE_SIZE = 65536
133 ## Use a small 8K stack
135 default STACK_SIZE=0x2000
138 ## Use a small 32K heap
140 default HEAP_SIZE=0x8000
144 ### Compute the location and size of where this firmware image
145 ### (linuxBIOS plus bootloader) will live in the boot rom chip.
147 default FALLBACK_SIZE=131072
150 ## LinuxBIOS C code runs at this location in RAM
152 default _RAMBASE=0x00004000
155 ## Load the payload from the ROM
157 default CONFIG_ROM_STREAM=1
161 ### Defaults of options that you may want to override in the target config file
165 ## The default compiler
167 default CC="$(CROSS_COMPILE)gcc -m32"
171 ## Disable the gdb stub by default
173 default CONFIG_GDB_STUB=0
176 ## The Serial Console
179 # To Enable the Serial Console
180 default CONFIG_CONSOLE_SERIAL8250=1
182 ## Select the serial console baud rate
183 default TTYS0_BAUD=115200
184 #default TTYS0_BAUD=57600
185 #default TTYS0_BAUD=38400
186 #default TTYS0_BAUD=19200
187 #default TTYS0_BAUD=9600
188 #default TTYS0_BAUD=4800
189 #default TTYS0_BAUD=2400
190 #default TTYS0_BAUD=1200
192 # Select the serial console base port
193 default TTYS0_BASE=0x3f8
195 # Select the serial protocol
196 # This defaults to 8 data bits, 1 stop bit, and no parity
197 default TTYS0_LCS=0x3
200 ### Select the linuxBIOS loglevel
202 ## EMERG 1 system is unusable
203 ## ALERT 2 action must be taken immediately
204 ## CRIT 3 critical conditions
205 ## ERR 4 error conditions
206 ## WARNING 5 warning conditions
207 ## NOTICE 6 normal but significant condition
208 ## INFO 7 informational
209 ## DEBUG 8 debug-level messages
210 ## SPEW 9 Way too many details
212 ## Request this level of debugging output
213 default DEFAULT_CONSOLE_LOGLEVEL=8
214 ## At a maximum only compile in this level of debugging
215 default MAXIMUM_CONSOLE_LOGLEVEL=8
218 ## Select power on after power fail setting
219 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
222 ## Don't enable the btext console
224 default CONFIG_CONSOLE_BTEXT=0