2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
26 #include <cpu/amd/amdfam10_sysconf.h>
27 #include "agesawrapper.h"
30 /* Global variables for MB layouts and these will be shared by irqtable mptable
31 * and acpi_tables busnum is default.
38 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
39 * You may need to preset pci1234 for HTIO board,
40 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
47 * HT Chain device num, actually it is unit id base of every ht device in chain,
48 * assume every chain only have 4 ht device at most
59 static u32 get_bus_conf_done = 0;
62 void get_bus_conf(void)
69 if (get_bus_conf_done == 1)
70 return; /* do it only once */
72 get_bus_conf_done = 1;
75 * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
76 * but functionally within the coreboot model, this is the best place to make the
77 * call. The logically correct place to call AmdInitLate is after PCI scan is done,
78 * after the decision about S3 resume is made, and before the system tables are
79 * written into RAM. The routine that is responsible for writing the tables is
80 * "write_tables", called near the end of "hardwaremain". There is no platform
81 * specific entry point between the S3 resume decision point and the call to
82 * "write_tables", and the next platform specific entry points are the calls to
83 * the ACPI table write functions. The first of ose would seem to be the right
84 * place, but other table write functions, e.g. the PIRQ table write function, are
85 * called before the ACPI tables are written. This routine is called at the beginning
86 * of each of the write functions called prior to the ACPI write functions, so this
87 * becomes the best place for this call.
89 status = agesawrapper_amdinitlate();
91 printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
96 for (i = 0; i < 0; i++) {
99 for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
103 for (i = 0; i < 256; i++) {
104 bus_type[i] = 0; /* default ISA bus. */
107 bus_type[0] = 1; /* pci */
109 bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff;
110 // bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
111 bus_sp5100[0] = bus_sr5650[0];
114 dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
117 bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
119 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
121 for (j = bus_sp5100[1]; j < bus_isa; j++)
126 for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
127 dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
129 bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
130 if(255 != bus_sr5650[i]) {
131 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
133 bus_type[bus_sr5650[i]] = 1; /* PCI bus. */
139 for (i = 0; i < 4; i++) {
140 dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
142 bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
143 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
147 for (j = bus_sp5100[2]; j < bus_isa; j++)
152 /* I/O APICs: APIC ID Version State Address */