src/mainboard/sunw/ultra40/romstage.c

   1 #define K8_ALLOCATE_IO_RANGE 1
   2
   3 #define QRANK_DIMM_SUPPORT 1
   4
   5 #if CONFIG_LOGICAL_CPUS==1
   6 #define SET_NB_CFG_54 1
   7 #endif
   8
   9
  10 #include <stdint.h>
  11 #include <string.h>
  12 #include <device/pci_def.h>
  13 #include <arch/io.h>
  14 #include <device/pnp_def.h>
  15 #include <arch/romcc_io.h>
  16 #include <cpu/x86/lapic.h>
  17 #include "option_table.h"
  18 #include "pc80/mc146818rtc_early.c"
  19 #include <console/console.h>
  20 #include "lib/ramtest.c"
  21
  22 #include <cpu/amd/model_fxx_rev.h>
  23 #include "northbridge/amd/amdk8/incoherent_ht.c"
  24 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  25 #include "northbridge/amd/amdk8/raminit.h"
  26 #include "cpu/amd/model_fxx/apic_timer.c"
  27 #include "lib/delay.c"
  28
  29 #include "cpu/x86/lapic/boot_cpu.c"
  30 #include "northbridge/amd/amdk8/reset_test.c"
  31 #include "northbridge/amd/amdk8/debug.c"
  32 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  33
  34 #include "cpu/x86/mtrr/earlymtrr.c"
  35 #include "cpu/x86/bist.h"
  36
  37 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  38
  39 #include "northbridge/amd/amdk8/setup_resource_map.c"
  40
  41 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  42
  43 static void memreset(int controllers, const struct mem_controller *ctrl)
  44 {
  45 }
  46
  47 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  48
  49 #define SUPERIO_GPIO_IO_BASE 0x400
  50
  51 #ifdef ENABLE_ONBOARD_SCSI
  52 static void sio_gpio_setup(void)
  53 {
  54         unsigned value;
  55
  56         /*Enable onboard scsi*/
  57         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  58         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  59         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  60 }
  61 #endif
  62
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65         /* nothing to do */
  66 }
  67
  68 static inline int spd_read_byte(unsigned device, unsigned address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #include "northbridge/amd/amdk8/raminit.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76
  77  /* tyan does not want the default */
  78 #include "resourcemap.c"
  79
  80 #include "cpu/amd/dualcore/dualcore.c"
  81
  82 #define CK804_NUM 2
  83 #define CK804_USE_NIC 1
  84 #define CK804_USE_ACI 1
  85
  86 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  87
  88 //set GPIO to input mode
  89 #define CK804_MB_SETUP \
  90                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  91                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  92                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  93                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  94                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  95                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  96
  97 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  98
  99
 100
 101 #include "cpu/amd/car/post_cache_as_ram.c"
 102
 103 #include "cpu/amd/model_fxx/init_cpus.c"
 104
 105 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 106 #include "northbridge/amd/amdk8/early_ht.c"
 107
 108 static void sio_setup(void)
 109 {
 110         unsigned value;
 111         uint32_t dword;
 112         uint8_t byte;
 113
 114         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 115
 116         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 117         byte |= 0x20;
 118         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 119
 120         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 121         dword |= (1<<29)|(1<<0);
 122         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 123
 124         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 125
 126         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 127         value &= 0xbf;
 128         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 129 }
 130
 131 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 132 {
 133         static const uint16_t spd_addr [] = {
 134                         // Node 0
 135                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 136                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 137                         // Node 1
 138                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 139                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 140         };
 141
 142         int needs_reset;
 143         unsigned bsp_apicid = 0;
 144
 145         struct mem_controller ctrl[8];
 146         unsigned nodes;
 147
 148         if (!cpu_init_detectedx && boot_cpu()) {
 149                 /* Nothing special needs to be done to find bus 0 */
 150                 /* Allow the HT devices to be found */
 151
 152                 enumerate_ht_chain();
 153
 154                 sio_setup();
 155
 156                 /* Setup the ck804 */
 157                 ck804_enable_rom();
 158         }
 159
 160         if (bist == 0) {
 161                 bsp_apicid = init_cpus(cpu_init_detectedx);
 162         }
 163
 164         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 165         uart_init();
 166         console_init();
 167
 168         /* Halt if there was a built in self test failure */
 169         report_bist_failure(bist);
 170
 171         setup_ultra40_resource_map();
 172
 173         needs_reset = setup_coherent_ht_domain();
 174
 175         wait_all_core0_started();
 176 #if CONFIG_LOGICAL_CPUS==1
 177         // It is said that we should start core1 after all core0 launched
 178         start_other_cores();
 179         wait_all_other_cores_started(bsp_apicid);
 180 #endif
 181
 182         needs_reset |= ht_setup_chains_x();
 183
 184         needs_reset |= ck804_early_setup_x();
 185
 186         if (needs_reset) {
 187                 print_info("ht reset -\n");
 188                 soft_reset();
 189         }
 190
 191         allow_all_aps_stop(bsp_apicid);
 192
 193         nodes = get_nodes();
 194         //It's the time to set ctrl now;
 195         fill_mem_ctrl(nodes, ctrl, spd_addr);
 196
 197         enable_smbus();
 198
 199         sdram_initialize(nodes, ctrl);
 200
 201         post_cache_as_ram();
 202 }
 203