2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define RAMINIT_SYSINFO 1
27 #define K8_ALLOCATE_IO_RANGE 1
28 //#define K8_SCAN_PCI_BUS 1
31 #define QRANK_DIMM_SUPPORT 1
33 #if CONFIG_LOGICAL_CPUS==1
34 #define SET_NB_CFG_54 1
37 //used by init_cpus and fidvid
38 #define K8_SET_FIDVID 0
39 //if we want to wait for core1 done before DQS training, set it to 0
40 #define K8_SET_FIDVID_CORE0_ONLY 1
42 #if CONFIG_K8_REV_F_SUPPORT == 1
43 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
46 #define DBGP_DEFAULT 7
50 #include <device/pci_def.h>
51 #include <device/pci_ids.h>
53 #include <device/pnp_def.h>
54 #include <arch/romcc_io.h>
55 #include <cpu/x86/lapic.h>
56 #include "option_table.h"
57 #include "pc80/mc146818rtc_early.c"
59 #if CONFIG_USE_FAILOVER_IMAGE==0
60 #include "pc80/serial.c"
61 #include "arch/i386/lib/console.c"
62 #if CONFIG_USBDEBUG_DIRECT
63 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
64 #include "pc80/usbdebug_direct_serial.c"
66 #include "ram/ramtest.c"
68 #include <cpu/amd/model_fxx_rev.h>
70 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
71 #include "northbridge/amd/amdk8/raminit.h"
72 #include "cpu/amd/model_fxx/apic_timer.c"
73 #include "lib/delay.c"
77 #include "cpu/x86/lapic/boot_cpu.c"
78 #include "northbridge/amd/amdk8/reset_test.c"
79 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
80 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
82 #if CONFIG_USE_FAILOVER_IMAGE==0
84 #include "cpu/x86/bist.h"
86 #include "northbridge/amd/amdk8/debug.c"
88 #include "cpu/amd/mtrr/amd_earlymtrr.c"
90 #include "northbridge/amd/amdk8/setup_resource_map.c"
92 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
94 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
96 static void memreset_setup(void)
100 static void memreset(int controllers, const struct mem_controller *ctrl)
104 static inline void activate_spd_rom(const struct mem_controller *ctrl)
109 static inline int spd_read_byte(unsigned device, unsigned address)
111 return smbus_read_byte(device, address);
114 #include "northbridge/amd/amdk8/amdk8_f.h"
115 #include "northbridge/amd/amdk8/coherent_ht.c"
117 #include "northbridge/amd/amdk8/incoherent_ht.c"
119 #include "northbridge/amd/amdk8/raminit_f.c"
121 #include "sdram/generic_sdram.c"
123 #include "resourcemap.c"
125 #include "cpu/amd/dualcore/dualcore.c"
128 #define MCP55_USE_NIC 1
129 #define MCP55_USE_AZA 1
131 #define MCP55_PCI_E_X_0 2
132 #define MCP55_PCI_E_X_1 4
134 #define MCP55_MB_SETUP \
135 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
136 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
137 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
138 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
139 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
140 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
142 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
143 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
145 #include "cpu/amd/car/copy_and_run.c"
147 #include "cpu/amd/car/post_cache_as_ram.c"
149 #include "cpu/amd/model_fxx/init_cpus.c"
151 #include "cpu/amd/model_fxx/fidvid.c"
155 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
157 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
158 #include "northbridge/amd/amdk8/early_ht.c"
161 static void sio_setup(void)
168 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
170 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
172 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
174 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
176 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
178 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
182 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
184 unsigned last_boot_normal_x = last_boot_normal();
186 /* Is this a cpu only reset? or Is this a secondary cpu? */
187 if ((cpu_init_detectedx) || (!boot_cpu())) {
188 if (last_boot_normal_x) {
195 /* Nothing special needs to be done to find bus 0 */
196 /* Allow the HT devices to be found */
198 enumerate_ht_chain();
202 /* Setup the mcp55 */
205 /* Is this a deliberate reset by the bios */
206 if (bios_reset_detected() && last_boot_normal_x) {
209 /* This is the primary cpu how should I boot? */
210 else if (do_normal_boot()) {
217 __asm__ volatile ("jmp __normal_image"
219 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
223 #if CONFIG_HAVE_FAILOVER_BOOT==1
224 __asm__ volatile ("jmp __fallback_image"
226 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
232 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
234 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
236 #if CONFIG_HAVE_FAILOVER_BOOT==1
237 #if CONFIG_USE_FAILOVER_IMAGE==1
238 failover_process(bist, cpu_init_detectedx);
240 real_main(bist, cpu_init_detectedx);
243 #if CONFIG_USE_FALLBACK_IMAGE == 1
244 failover_process(bist, cpu_init_detectedx);
246 real_main(bist, cpu_init_detectedx);
250 #if CONFIG_USE_FAILOVER_IMAGE==0
252 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
254 static const uint16_t spd_addr [] = {
255 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
256 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
257 #if CONFIG_MAX_PHYSICAL_CPUS > 1
258 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
259 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
263 struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
266 unsigned bsp_apicid = 0;
269 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
272 pnp_enter_ext_func_mode(SERIAL_DEV);
273 pnp_write_config(SERIAL_DEV, 0x24, 0);
274 w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
275 pnp_exit_ext_func_mode(SERIAL_DEV);
277 setup_mb_resource_map();
281 /* Halt if there was a built in self test failure */
282 report_bist_failure(bist);
285 #if CONFIG_USBDEBUG_DIRECT
286 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
287 early_usbdebug_direct_init();
290 print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
292 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
294 #if CONFIG_MEM_TRAIN_SEQ == 1
295 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
297 setup_coherent_ht_domain(); // routing table and start other core0
299 wait_all_core0_started();
300 #if CONFIG_LOGICAL_CPUS==1
301 // It is said that we should start core1 after all core0 launched
302 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
303 * So here need to make sure last core0 is started, esp for two way system,
304 * (there may be apic id conflicts in that case)
307 wait_all_other_cores_started(bsp_apicid);
310 /* it will set up chains and store link pair for optimization later */
311 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
313 #if K8_SET_FIDVID == 1
317 msr=rdmsr(0xc0010042);
318 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
324 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
326 init_fidvid_bsp(bsp_apicid);
328 // show final fid and vid
331 msr=rdmsr(0xc0010042);
332 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
337 needs_reset |= optimize_link_coherent_ht();
338 needs_reset |= optimize_link_incoherent_ht(sysinfo);
339 needs_reset |= mcp55_early_setup_x();
341 // fidvid change will issue one LDTSTOP and the HT change will be effective too
343 print_info("ht reset -\r\n");
346 allow_all_aps_stop(bsp_apicid);
348 //It's the time to set ctrl in sysinfo now;
349 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
355 //do we need apci timer, tsc...., only debug need it for better output
356 /* all ap stopped? */
357 // init_timer(); // Need to use TMICT to synconize FID/VID
359 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
361 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now