2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
22 default CONFIG_XIP_ROM_SIZE = 64 * 1024
23 include /config/failovercalculation.lb
28 object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
29 if CONFIG_HAVE_MP_TABLE object mptable.o end
30 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
34 makerule ./cache_as_ram_auto.o
35 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
36 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
39 makerule ./cache_as_ram_auto.inc
40 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
41 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
42 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
43 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
47 if CONFIG_USE_FAILOVER_IMAGE
49 if CONFIG_AP_CODE_IN_CAR
51 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
52 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
54 ldscript /arch/i386/init/ldscript_apc.lb
58 if CONFIG_HAVE_FAILOVER_BOOT
59 if CONFIG_USE_FAILOVER_IMAGE
60 mainboardinit cpu/x86/16bit/entry16.inc
61 ldscript /cpu/x86/16bit/entry16.lds
64 if CONFIG_USE_FALLBACK_IMAGE
65 mainboardinit cpu/x86/16bit/entry16.inc
66 ldscript /cpu/x86/16bit/entry16.lds
70 mainboardinit cpu/x86/32bit/entry32.inc
73 ldscript /cpu/x86/32bit/entry32.lds
76 ldscript /cpu/amd/car/cache_as_ram.lds
79 if CONFIG_HAVE_FAILOVER_BOOT
80 if CONFIG_USE_FAILOVER_IMAGE
81 mainboardinit cpu/x86/16bit/reset16.inc
82 ldscript /cpu/x86/16bit/reset16.lds
84 mainboardinit cpu/x86/32bit/reset32.inc
85 ldscript /cpu/x86/32bit/reset32.lds
88 if CONFIG_USE_FALLBACK_IMAGE
89 mainboardinit cpu/x86/16bit/reset16.inc
90 ldscript /cpu/x86/16bit/reset16.lds
92 mainboardinit cpu/x86/32bit/reset32.inc
93 ldscript /cpu/x86/32bit/reset32.lds
97 mainboardinit southbridge/nvidia/mcp55/id.inc
98 ldscript /southbridge/nvidia/mcp55/id.lds
100 # ROMSTRAP table for MCP55.
101 if CONFIG_HAVE_FAILOVER_BOOT
102 if CONFIG_USE_FAILOVER_IMAGE
103 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
104 ldscript /southbridge/nvidia/mcp55/romstrap.lds
107 if CONFIG_USE_FALLBACK_IMAGE
108 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
109 ldscript /southbridge/nvidia/mcp55/romstrap.lds
113 mainboardinit cpu/amd/car/cache_as_ram.inc
115 if CONFIG_HAVE_FAILOVER_BOOT
116 if CONFIG_USE_FAILOVER_IMAGE
117 ldscript /arch/i386/lib/failover_failover.lds
120 if CONFIG_USE_FALLBACK_IMAGE
121 ldscript /arch/i386/lib/failover.lds
126 initobject cache_as_ram_auto.o
128 mainboardinit ./cache_as_ram_auto.inc
133 chip northbridge/amd/amdk8/root_complex # Root complex
134 device apic_cluster 0 on # APIC cluster
135 chip cpu/amd/socket_AM2 # CPU
136 device apic 0 on end # APIC
139 device pci_domain 0 on # PCI domain
140 chip northbridge/amd/amdk8 # Northbridge / mc0
142 # Devices on link 0, link 0 == LDT 0
143 chip southbridge/nvidia/mcp55 # Southbridge
144 device pci 0.0 on end # HT
145 device pci 1.0 on # LPC
146 chip superio/winbond/w83627ehg # Super I/O
147 device pnp 4e.0 on # Floppy
152 device pnp 4e.1 on # Parallel port
156 device pnp 4e.2 on # Com1
160 device pnp 4e.3 on # Com2 / IrDA
164 device pnp 4e.5 on # PS/2 keyboard
167 irq 0x70 = 1 # PS/2 keyboard IRQ
168 irq 0x72 = 12 # PS/2 mouse IRQ
170 device pnp 4e.6 off # Serial flash interface
173 device pnp 4e.7 off # GPIO1/6, game port, MIDI port
174 # io 0x60 = 0x220 # Datasheet: 0x201
175 # io 0x62 = 0x300 # Datasheet: 0x330
178 device pnp 4e.8 off # WDTO#, PLED
180 device pnp 4e.9 off # GPIO2/3/4/5, SUSLED
182 device pnp 4e.a off # ACPI
184 device pnp 4e.b on # HWM (for lm-sensors)
189 device pci 1.1 on # SM 0
190 chip drivers/generic/generic # DIMM 0-0-0
193 chip drivers/generic/generic # DIMM 0-0-1
196 chip drivers/generic/generic # DIMM 0-1-0
199 chip drivers/generic/generic # DIMM 0-1-1
203 # chip drivers/generic/generic # DIMM 1-0-0
204 # device i2c 54 on end
206 # chip drivers/generic/generic # DIMM 1-0-1
207 # device i2c 55 on end
209 # chip drivers/generic/generic # DIMM 1-1-0
210 # device i2c 56 on end
212 # chip drivers/generic/generic # DIMM 1-1-1
213 # device i2c 57 on end
216 # TODO: Check if the stuff below is correct / needed.
217 device pci 1.1 on # SM 1
218 # PCI device SMBus address will depend on addon PCI device,
219 # do we need to scan_smbus_bus?
221 # chip drivers/generic/generic # PCIXA Slot1
222 # device i2c 50 on end
224 # chip drivers/generic/generic # PCIXB Slot1
225 # device i2c 51 on end
227 # chip drivers/generic/generic # PCIXB Slot2
228 # device i2c 52 on end
230 # chip drivers/generic/generic # PCI Slot1
231 # device i2c 53 on end
233 # chip drivers/generic/generic # Master MCP55 PCI-E
234 # device i2c 54 on end
236 # chip drivers/generic/generic # Slave MCP55 PCI-E
237 # device i2c 55 on end
239 chip drivers/generic/generic # MAC EEPROM
243 device pci 2.0 on end # USB 1.1
244 device pci 2.1 on end # USB 2
245 device pci 4.0 on end # IDE
246 device pci 5.0 on end # SATA 0
247 device pci 5.1 on end # SATA 1
248 device pci 5.2 off end # SATA 2 (N/A on this board)
249 device pci 6.0 on end # PCI
250 device pci 6.1 on end # AZA (HD Audio)
251 device pci 8.0 on end # NIC
252 device pci 9.0 off end # NIC (N/A on this board)
253 device pci a.0 off end # PCI E 5 (N/A on this board?)
254 device pci b.0 on end # PCI E 4
255 device pci c.0 on end # PCI E 3
256 device pci d.0 on end # PCI E 2
257 device pci e.0 on end # PCI E 1
258 device pci f.0 on end # PCI E 0
259 register "ide0_enable" = "1"
260 register "sata0_enable" = "1"
261 register "sata1_enable" = "1"
262 # TODO: Check the two lines below.
263 register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
264 register "mac_eeprom_addr" = "0x51"
267 device pci 18.0 on end # Link 1
268 device pci 18.0 on end
269 device pci 18.1 on end
270 device pci 18.2 on end
271 device pci 18.3 on end
276 # chip drivers/generic/debug
277 # device pnp 0.0 off end # chip name
278 # device pnp 0.1 on end # pci_regs_all
279 # device pnp 0.2 on end # mem
280 # device pnp 0.3 off end # cpuid
281 # device pnp 0.4 on end # smbus_regs_all
282 # device pnp 0.5 off end # dual core msr
283 # device pnp 0.6 off end # cache size
284 # device pnp 0.7 off end # tsc
285 # device pnp 0.8 off end # io
286 # device pnp 0.9 off end # io