2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Tyan
5 * Copyright (C) 2006 AMD
6 * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
8 * Copyright (C) 2007 University of Mannheim
9 * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
10 * Copyright (C) 2009 University of Heidelberg
11 * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define RAMINIT_SYSINFO 1
30 #define FAM10_SCAN_PCI_BUS 0
31 #define FAM10_ALLOCATE_IO_RANGE 1
33 #define QRANK_DIMM_SUPPORT 1
35 #if CONFIG_LOGICAL_CPUS==1
36 #define SET_NB_CFG_54 1
40 #define SET_FIDVID_CORE_RANGE 0
44 #include <device/pci_def.h>
45 #include <device/pci_ids.h>
47 #include <device/pnp_def.h>
48 #include <arch/romcc_io.h>
49 #include <cpu/x86/lapic.h>
50 #include "option_table.h"
51 #include <console/console.h>
52 #include <cpu/amd/model_10xxx_rev.h>
53 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
54 #include "northbridge/amd/amdfam10/raminit.h"
55 #include "northbridge/amd/amdfam10/amdfam10.h"
58 #include "cpu/amd/model_10xxx/apic_timer.c"
59 #include "lib/delay.c"
60 #include "cpu/x86/lapic/boot_cpu.c"
61 #include "northbridge/amd/amdfam10/reset_test.c"
63 #include "superio/serverengines/pilot/pilot_early_serial.c"
64 #include "superio/serverengines/pilot/pilot_early_init.c"
65 #include "superio/nsc/pc87417/pc87417_early_serial.c"
67 #include "cpu/x86/bist.h"
69 #include "northbridge/amd/amdfam10/debug.c"
71 #include "cpu/x86/mtrr/earlymtrr.c"
73 //#include "northbridge/amd/amdfam10/setup_resource_map.c"
75 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
76 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
78 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
80 static inline void activate_spd_rom(const struct mem_controller *ctrl)
88 outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
91 static inline int spd_read_byte(unsigned device, unsigned address)
93 return smbus_read_byte(device, address);
96 #include "northbridge/amd/amdfam10/amdfam10.h"
98 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
99 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
101 #include "cpu/amd/quadcore/quadcore.c"
103 #include "cpu/amd/car/post_cache_as_ram.c"
105 #include "cpu/amd/microcode/microcode.c"
106 #include "cpu/amd/model_10xxx/update_microcode.c"
107 #include "cpu/amd/model_10xxx/init_cpus.c"
109 #include "northbridge/amd/amdfam10/early_ht.c"
111 #include "spd_addr.h"
113 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
115 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
122 if (!cpu_init_detectedx && boot_cpu()) {
123 /* Nothing special needs to be done to find bus 0 */
124 /* Allow the HT devices to be found */
125 /* mov bsp to bus 0xff when > 8 nodes */
126 set_bsp_node_CHtExtNodeCfgEn();
127 enumerate_ht_chain();
129 /* Setup the rom access for 4M */
130 bcm5785_enable_rom();
131 bcm5785_enable_lpc();
133 pc87417_enable_dev(RTC_DEV);
139 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
142 pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
146 /* Halt if there was a built in self test failure */
147 report_bist_failure(bist);
150 pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
153 printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
154 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
155 printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
156 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
158 /* Setup sysinfo defaults */
159 set_sysinfo_in_ram(0);
161 update_microcode(val);
167 amd_ht_init(sysinfo);
170 /* Setup nodes PCI space and start core 0 AP init. */
171 finalize_node_setup(sysinfo);
175 /* wait for all the APs core0 started by finalize_node_setup. */
176 /* FIXME: A bunch of cores are going to start output to serial at once.
177 * It would be nice to fixup prink spinlocks for ROM XIP mode.
178 * I think it could be done by putting the spinlock flag in the cache
179 * of the BSP located right after sysinfo.
182 wait_all_core0_started();
184 #if CONFIG_LOGICAL_CPUS==1
185 /* Core0 on each node is configured. Now setup any additional cores. */
186 printk(BIOS_DEBUG, "start_other_cores()\n");
189 wait_all_other_cores_started(bsp_apicid);
193 msr = rdmsr(0xc0010071);
194 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
196 /* FIXME: The sb fid change may survive the warm reset and only
197 * need to be done once.*/
199 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
203 if (!warm_reset_detect(0)) { // BSP is node 0
204 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
206 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
211 /* show final fid and vid */
212 msr=rdmsr(0xc0010071);
213 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
218 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
219 if (!warm_reset_detect(0)) {
220 print_info("...WARM RESET...\n\n\n");
222 die("After soft_reset_x - shouldn't see this message!!!\n");
225 /* It's the time to set ctrl in sysinfo now; */
226 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
229 //do we need apci timer, tsc...., only debug need it for better output
230 /* all ap stopped? */
231 // init_timer(); // Need to use TMICT to synconize FID/VID
233 printk(BIOS_DEBUG, "raminit_amdmct()\n");
234 raminit_amdmct(sysinfo);
237 bcm5785_early_setup();