src/mainboard/gigabyte/ga_2761gxdk/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   7 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
   8 ##
   9 ## This program is free software; you can redistribute it and/or modify
  10 ## it under the terms of the GNU General Public License as published by
  11 ## the Free Software Foundation; either version 2 of the License, or
  12 ## (at your option) any later version.
  13 ##
  14 ## This program is distributed in the hope that it will be useful,
  15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ## GNU General Public License for more details.
  18 ##
  19 ## You should have received a copy of the GNU General Public License
  20 ## along with this program; if not, write to the Free Software
  21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 ##
  23
  24 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  25 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  26 include /config/failovercalculation.lb
  27
  28 arch i386 end
  29
  30 ##
  31 ## Build the objects we have code for in this directory.
  32 ##
  33
  34 driver mainboard.o
  35 #needed by irq_tables and mptable and acpi_tables
  36 object get_bus_conf.o
  37
  38 if CONFIG_HAVE_MP_TABLE object mptable.o end
  39 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
  40 #object reset.o
  41
  42         if CONFIG_USE_INIT
  43                 makerule ./cache_as_ram_auto.o
  44                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  45                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  46                 end
  47         else
  48                 makerule ./cache_as_ram_auto.inc
  49                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  50                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  51                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  52                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  53                 end
  54         end
  55
  56 if CONFIG_USE_FAILOVER_IMAGE
  57 else
  58     if CONFIG_AP_CODE_IN_CAR
  59         makerule ./apc_auto.o
  60                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  61                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  62         end
  63         ldscript /arch/i386/init/ldscript_apc.lb
  64     end
  65 end
  66
  67
  68 ##
  69 ## Build our 16 bit and 32 bit coreboot entry code
  70 ##
  71 if CONFIG_HAVE_FAILOVER_BOOT
  72     if CONFIG_USE_FAILOVER_IMAGE
  73         mainboardinit cpu/x86/16bit/entry16.inc
  74         ldscript /cpu/x86/16bit/entry16.lds
  75     end
  76 else
  77     if CONFIG_USE_FALLBACK_IMAGE
  78         mainboardinit cpu/x86/16bit/entry16.inc
  79         ldscript /cpu/x86/16bit/entry16.lds
  80     end
  81 end
  82
  83 mainboardinit cpu/x86/32bit/entry32.inc
  84
  85         if CONFIG_USE_INIT
  86                 ldscript /cpu/x86/32bit/entry32.lds
  87         end
  88
  89         if CONFIG_USE_INIT
  90                 ldscript /cpu/amd/car/cache_as_ram.lds
  91         end
  92
  93 ##
  94 ## Build our reset vector (This is where coreboot is entered)
  95 ##
  96 if CONFIG_HAVE_FAILOVER_BOOT
  97     if CONFIG_USE_FAILOVER_IMAGE
  98         mainboardinit cpu/x86/16bit/reset16.inc
  99         ldscript /cpu/x86/16bit/reset16.lds
 100     else
 101         mainboardinit cpu/x86/32bit/reset32.inc
 102         ldscript /cpu/x86/32bit/reset32.lds
 103     end
 104 else
 105     if CONFIG_USE_FALLBACK_IMAGE
 106         mainboardinit cpu/x86/16bit/reset16.inc
 107         ldscript /cpu/x86/16bit/reset16.lds
 108     else
 109         mainboardinit cpu/x86/32bit/reset32.inc
 110         ldscript /cpu/x86/32bit/reset32.lds
 111     end
 112 end
 113
 114 ##
 115 ## Include an id string (For safe flashing)
 116 ##
 117 mainboardinit southbridge/sis/sis966/id.inc
 118 ldscript /southbridge/sis/sis966/id.lds
 119
 120 ##
 121 ## ROMSTRAP table for MCP55
 122 ##
 123 if CONFIG_HAVE_FAILOVER_BOOT
 124     if CONFIG_USE_FAILOVER_IMAGE
 125         mainboardinit southbridge/sis/sis966/romstrap.inc
 126         ldscript /southbridge/sis/sis966/romstrap.lds
 127     end
 128 else
 129     if CONFIG_USE_FALLBACK_IMAGE
 130         mainboardinit southbridge/sis/sis966/romstrap.inc
 131         ldscript /southbridge/sis/sis966/romstrap.lds
 132     end
 133 end
 134
 135         ##
 136         ## Setup Cache-As-Ram
 137         ##
 138         mainboardinit cpu/amd/car/cache_as_ram.inc
 139
 140 ###
 141 ### This is the early phase of coreboot startup
 142 ### Things are delicate and we test to see if we should
 143 ### failover to another image.
 144 ###
 145 if CONFIG_HAVE_FAILOVER_BOOT
 146     if CONFIG_USE_FAILOVER_IMAGE
 147                 ldscript /arch/i386/lib/failover_failover.lds
 148     end
 149 else
 150     if CONFIG_USE_FALLBACK_IMAGE
 151                 ldscript /arch/i386/lib/failover.lds
 152     end
 153 end
 154
 155 ##
 156 ## Setup RAM
 157 ##
 158         if CONFIG_USE_INIT
 159                 initobject cache_as_ram_auto.o
 160         else
 161                 mainboardinit ./cache_as_ram_auto.inc
 162         end
 163
 164 ##
 165 ## Include the secondary Configuration files
 166 ##
 167 config chip.h
 168
 169 chip northbridge/amd/amdk8/root_complex
 170         device apic_cluster 0 on
 171                 chip cpu/amd/socket_AM2
 172                         device apic 0 on end
 173                 end
 174         end
 175         device pci_domain 0 on
 176                 chip northbridge/amd/amdk8 #mc0
 177                         device pci 18.0 on
 178                                 #  devices on link 0, link 0 == LDT 0
 179                                 chip southbridge/sis/sis966
 180                                         device pci 0.0 on end   # Northbridge
 181                                         device pci 1.0 on               # AGP bridge
 182                                           chip drivers/pci/onboard      # Integrated VGA
 183                                                 device pci 0.0 on end
 184                                                 register "rom_address" = "0xfff80000"
 185                                           end
 186                                         end
 187                                         device pci 2.0 on # LPC
 188                                                 chip superio/ite/it8716f
 189                                                         device pnp 2e.0 off #  Floppy (N/A)
 190                                                                 io 0x60 = 0x3f0
 191                                                                 irq 0x70 = 6
 192                                                                 drq 0x74 = 2
 193                                                         end
 194                                                         device pnp 2e.1 on #  Com1
 195                                                                 io 0x60 = 0x3f8
 196                                                                 irq 0x70 = 4
 197                                                         end
 198                                                         device pnp 2e.2 off #  Com2 (N/A)
 199                                                                 io 0x60 = 0x2f8
 200                                                                 irq 0x70 = 3
 201                                                         end
 202                                                         device pnp 2e.3 off #  Parallel port (N/A)
 203                                                                 io 0x60 = 0x378
 204                                                                 irq 0x70 = 7
 205                                                         end
 206                                                         device pnp 2e.4 on #  EC
 207                                                                 io 0x60 = 0x290
 208                                                                 io 0x62 = 0x230
 209                                                                 irq 0x70 = 9
 210                                                         end
 211                                                         device pnp 2e.5 off #  PS/2 keyboard (N/A)
 212                                                                 io 0x60 = 0x60
 213                                                                 io 0x62 = 0x64
 214                                                                 irq 0x70 = 1
 215                                                         end
 216                                                         device pnp 2e.6 off #  Mouse (N/A)
 217                                                                 irq 0x70 = 12
 218                                                         end
 219                                                         device pnp 2e.8 off #  MIDI (N/A)
 220                                                                 io 0x60 = 0x300
 221                                                                 irq 0x70 = 10
 222                                                         end
 223                                                         device pnp 2e.9 off #  GAME (N/A)
 224                                                                 io 0x60 = 0x220
 225                                                         end
 226                                                         device pnp 2e.a off end #  CIR (N/A)
 227                                                 end
 228                                         end
 229
 230                                         device pci 2.5 off end # IDE (SiS5513)
 231                                         device pci 2.6 off end # Modem (SiS7013)
 232                                         device pci 2.7 off end # Audio (SiS7012)
 233                                         device pci 3.0 on end # USB (SiS7001,USB1.1)
 234                                         device pci 3.1 on end # USB (SiS7001,USB1.1)
 235                                         device pci 3.3 on end # USB (SiS7002,USB2.0)
 236                                         device pci 4.0 on end # NIC (SiS191)
 237                                         device pci 5.0 on end # SATA (SiS1183,Native Mode)
 238                                         device pci 6.0 on end # PCI-e x1
 239                                         device pci 7.0 on end # PCI-e x1
 240                                         device pci a.0 off end
 241                                         device pci b.0 off end
 242                                         device pci c.0 off end
 243                                         device pci d.0 off end
 244                                         device pci e.0 off end
 245                                         device pci f.0 off end # HD Audio (SiS7502)
 246
 247                                         register "ide0_enable" = "1"
 248                                         register "ide1_enable" = "1"
 249                                         register "sata0_enable" = "1"
 250                                         register "sata1_enable" = "1"
 251                                 end
 252                         end #  device pci 18.0
 253                         device pci 18.0 on end # Link 1
 254                         device pci 18.0 on end
 255                         device pci 18.1 on end
 256                         device pci 18.2 on end
 257                         device pci 18.3 on end
 258                 end # mc0
 259
 260         end # PCI domain
 261
 262 #       chip drivers/generic/debug
 263 #               device pnp 0.0 off end # chip name
 264 #               device pnp 0.1 on end # pci_regs_all
 265 #               device pnp 0.2 off end # mem
 266 #               device pnp 0.3 off end # cpuid
 267 #               device pnp 0.4 off end # smbus_regs_all
 268 #               device pnp 0.5 off end # dual core msr
 269 #               device pnp 0.6 off end # cache size
 270 #               device pnp 0.7 off end # tsc
 271 #               device pnp 0.8 off end # io
 272 #               device pnp 0.9 off end # io
 273 #       end
 274 end #root_complex