2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 /* Configuration of the i945 driver */
23 #define CHIPSET_I945GM 1
24 #define CHANNEL_XOR_RANDOMIZATION 1
29 #include <arch/romcc_io.h>
30 #include <device/pci_def.h>
31 #include <device/pnp_def.h>
32 #include <cpu/x86/lapic.h>
34 #include <pc80/mc146818rtc.h>
36 #include <console/console.h>
37 #include <cpu/x86/bist.h>
40 #define DBGP_DEFAULT 0
41 #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
42 #include "pc80/usbdebug_serial.c"
45 #include "lib/ramtest.c"
46 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
48 #include "northbridge/intel/i945/udelay.c"
50 #include "southbridge/intel/i82801gx/i82801gx.h"
51 static void setup_ich7_gpios(void)
55 printk(BIOS_DEBUG, " GPIOS...");
56 /* General Registers */
57 outl(0x1f28f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
58 outl(0xe0e809c3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
59 // Power On value is eede1fbf, we set: (TODO explain why)
69 // We should probably do this explicitly bitwise, see below.
70 outl(0xeee83f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
71 /* Output Control Registers */
72 outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
73 /* Input Control Registers */
74 outl(0x00000180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
75 outl(0x000000e6, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
76 outl(0x000000d0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
77 outl(0x00000034, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
79 printk(BIOS_SPEW, "\n Initializing drive bay...\n");
80 gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
81 gpios |= (1 << 0); // GPIO33 = ODD
82 gpios |= (1 << 1); // GPIO34 = IDE_RST#
83 outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
85 gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
86 gpios &= ~(1 << 13); // ??
87 outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
89 printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n");
90 gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
91 gpios &= ~(1 << 24); // Enable LAN Power
92 outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
95 #include "northbridge/intel/i945/early_init.c"
97 static inline int spd_read_byte(unsigned device, unsigned address)
99 return smbus_read_byte(device, address);
102 #include "northbridge/intel/i945/raminit.h"
103 #include "northbridge/intel/i945/raminit.c"
104 #include "northbridge/intel/i945/errata.c"
105 #include "northbridge/intel/i945/debug.c"
107 static void ich7_enable_lpc(void)
110 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
112 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
114 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
115 // Enable 0x02e0 - 0x2ff
116 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
117 // Enable 0x600 - 0x6ff
118 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
119 // Enable 0x68 - 0x6f
120 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
124 /* This box has two superios, so enabling serial becomes slightly excessive.
125 * We disable a lot of stuff to make sure that there are no conflicts between
126 * the two. Also set up the GPIOs from the beginning. This is the "no schematic
127 * but safe anyways" method.
129 static void pnp_enter_ext_func_mode(device_t dev)
131 unsigned int port = dev >> 8;
135 static void pnp_exit_ext_func_mode(device_t dev)
137 unsigned int port = dev >> 8;
141 static void pnp_write_register(device_t dev, int reg, int val)
143 unsigned int port = dev >> 8;
148 static void early_superio_config(void)
152 dev=PNP_DEV(0x4e, 0x00);
154 pnp_enter_ext_func_mode(dev);
155 pnp_write_register(dev, 0x02, 0x0e); // UART power
156 pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
157 pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
158 pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
159 pnp_write_register(dev, 0x1e, 1); // no 32khz clock
160 pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
161 pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
162 pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
163 pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
165 pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR
166 pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
167 pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR
168 pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
169 pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR
170 pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
171 pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR
172 pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
174 pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT
175 pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT
176 pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT
177 pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR
178 pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL
179 pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1
180 pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2
181 pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3
183 pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5
184 pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6
185 pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7
186 pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8
187 pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9
188 pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10
190 pnp_exit_ext_func_mode(dev);
193 static void rcba_config(void)
195 /* Set up virtual channel 0 */
196 //RCBA32(0x0014) = 0x80000001;
197 //RCBA32(0x001c) = 0x03128010;
199 /* Device 1f interrupt pin register */
200 RCBA32(0x3100) = 0x00042220;
201 /* Device 1d interrupt pin register */
202 RCBA32(0x310c) = 0x00214321;
204 /* dev irq route register */
205 RCBA16(0x3140) = 0x0232;
206 RCBA16(0x3142) = 0x3246;
207 RCBA16(0x3144) = 0x0237;
208 RCBA16(0x3146) = 0x3201;
209 RCBA16(0x3148) = 0x3216;
212 RCBA8(0x31ff) = 0x03;
214 /* Enable upper 128bytes of CMOS */
215 RCBA32(0x3400) = (1 << 2);
217 /* Disable unused devices */
218 RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
219 RCBA32(0x3418) |= (1 << 0); // Required.
221 /* Enable PCIe Root Port Clock Gate */
222 // RCBA32(0x341c) = 0x00000001;
225 /* This should probably go into the ACPI enable trap */
226 /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
227 RCBA32(0x1e84) = 0x00020001;
228 RCBA32(0x1e80) = 0x0000fe01;
230 /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
231 RCBA32(0x1e9c) = 0x000200f0;
232 RCBA32(0x1e98) = 0x000c0801;
235 static void early_ich7_init(void)
240 // program secondary mlt XXX byte?
241 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
243 // reset rtc power status
244 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
246 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
248 // usb transient disconnect
249 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
251 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
253 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
254 reg32 |= (1 << 29) | (1 << 17);
255 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
257 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
258 reg32 |= (1 << 31) | (1 << 27);
259 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
261 RCBA32(0x0088) = 0x0011d000;
262 RCBA16(0x01fc) = 0x060f;
263 RCBA32(0x01f4) = 0x86000040;
264 RCBA32(0x0214) = 0x10030549;
265 RCBA32(0x0218) = 0x00020504;
266 RCBA8(0x0220) = 0xc5;
267 reg32 = RCBA32(0x3410);
269 RCBA32(0x3410) = reg32;
270 reg32 = RCBA32(0x3430);
273 RCBA32(0x3430) = reg32;
274 RCBA32(0x3418) |= (1 << 0);
275 RCBA16(0x0200) = 0x2008;
276 RCBA8(0x2027) = 0x0d;
277 RCBA16(0x3e08) |= (1 << 7);
278 RCBA16(0x3e48) |= (1 << 7);
279 RCBA32(0x3e0e) |= (1 << 7);
280 RCBA32(0x3e4e) |= (1 << 7);
282 // next step only on ich7m b0 and later:
283 reg32 = RCBA32(0x2034);
284 reg32 &= ~(0x0f << 16);
286 RCBA32(0x2034) = reg32;
291 // Now, this needs to be included because it relies on the symbol
292 // __PRE_RAM_ being set during CAR stage (in order to compile the
293 // BSS free versions of the functions). Either rewrite the code
294 // to be always BSS free, or invent a flag that's better suited than
295 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
297 #include "lib/cbmem.c"
299 void main(unsigned long bist)
310 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
312 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
316 early_superio_config();
318 /* Set up the console */
322 i82801gx_enable_usbdebug(DBGP_DEFAULT);
323 early_usbdebug_init();
327 /* Halt if there was a built in self test failure */
328 report_bist_failure(bist);
330 if (MCHBAR16(SSKPD) == 0xCAFE) {
331 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
333 while (1) asm("hlt");
336 /* Perform some early chipset initialization required
337 * before RAM initialization can work
339 i945_early_initialization();
342 reg32 = inl(DEFAULT_PMBASE + 0x04);
343 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
344 if (((reg32 >> 10) & 7) == 5) {
345 #if CONFIG_HAVE_ACPI_RESUME
346 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
348 /* Clear SLP_TYPE. This will break stage2 but
349 * we care for that when we get there.
351 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
354 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
358 /* Enable SPD ROMs and DDR-II DRAM */
361 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
362 dump_spd_registers();
365 sdram_initialize(boot_mode);
367 /* Perform some initialization that must run before stage2 */
370 /* This should probably go away. Until now it is required
371 * and mainboard specific
375 /* Chipset Errata! */
378 /* Initialize the internal PCIe links before we go into stage2 */
379 i945_late_initialization();
381 #if CONFIG_HAVE_ACPI_RESUME == 0
382 /* When doing resume, we must not overwrite RAM */
383 #if defined(DEBUG_RAM_SETUP)
384 sdram_dump_mchbar_registers();
387 /* This will not work if TSEG is in place! */
388 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
390 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
391 ram_check(0x00000000, 0x000a0000);
392 ram_check(0x00100000, tom);
396 MCHBAR16(SSKPD) = 0xCAFE;
398 #if CONFIG_HAVE_ACPI_RESUME
399 /* Start address of high memory tables */
400 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
402 /* If there is no high memory area, we didn't boot before, so
403 * this is not a resume. In that case we just create the cbmem toc.
405 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
406 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
408 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
409 * through stage 2. We could keep stuff like stack and heap in high tables
410 * memory completely, but that's a wonderful clean up task for another
413 if (resume_backup_memory)
414 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
416 /* Magic for S3 resume */
417 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);