2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
8 #include "pc80/serial.c"
9 #include <console/console.h>
10 #include "lib/ramtest.c"
11 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
12 #include "superio/nsc/pc97317/pc97317_early_serial.c"
13 //#include "northbridge/intel/i440bx/raminit.h"
14 #include "cpu/x86/bist.h"
15 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
17 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
19 //#include "lib/delay.c"
21 #include "northbridge/amd/gx1/raminit.c"
23 static void main(unsigned long bist)
25 pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
29 /* Halt if there was a built in self test failure */
30 report_bist_failure(bist);
36 /* Check all of memory */
38 ram_check(0x00000000, msr.lo);
44 /* Check 16MB of memory @ 0*/
45 { 0x00000000, 0x01000000 },
47 /* Check 16MB of memory @ 2GB */
48 { 0x80000000, 0x81000000 },
52 for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
53 ram_check(check_addrs[i].lo, check_addrs[i].hi);