1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
8 ## Build the objects we have code for in this directory.
15 if CONFIG_HAVE_MP_TABLE object mptable.o end
16 if CONFIG_HAVE_PIRQ_TABLE
25 makerule ./cache_as_ram_auto.o
26 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
27 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
32 makerule ./cache_as_ram_auto.inc
33 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
34 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
35 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
36 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
42 ## Build our 16 bit and 32 bit coreboot entry code
44 mainboardinit cpu/x86/16bit/entry16.inc
45 mainboardinit cpu/x86/32bit/entry32.inc
46 ldscript /cpu/x86/16bit/entry16.lds
48 ldscript /cpu/x86/32bit/entry32.lds
52 ldscript /cpu/amd/car/cache_as_ram.lds
56 ## Build our reset vector (This is where coreboot is entered)
58 if CONFIG_USE_FALLBACK_IMAGE
59 mainboardinit cpu/x86/16bit/reset16.inc
60 ldscript /cpu/x86/16bit/reset16.lds
62 mainboardinit cpu/x86/32bit/reset32.inc
63 ldscript /cpu/x86/32bit/reset32.lds
67 ## Include an id string (For safe flashing)
69 mainboardinit arch/i386/lib/id.inc
70 ldscript /arch/i386/lib/id.lds
75 mainboardinit cpu/amd/car/cache_as_ram.inc
78 ### This is the early phase of coreboot startup
79 ### Things are delicate and we test to see if we should
80 ### failover to another image.
82 if CONFIG_USE_FALLBACK_IMAGE
83 ldscript /arch/i386/lib/failover.lds
87 ### O.k. We aren't just an intermediary anymore!
94 initobject cache_as_ram_auto.o
96 mainboardinit ./cache_as_ram_auto.inc
100 ## Include the secondary Configuration files
104 # sample config for broadcom/blast
105 chip northbridge/amd/amdk8/root_complex
106 device apic_cluster 0 on
107 chip cpu/amd/socket_940
111 device pci_domain 0 on
112 chip northbridge/amd/amdk8
113 device pci 18.0 on # northbridge
115 chip southbridge/broadcom/bcm5780 # HT2000
116 device pci 0.0 on end # PXB 1 0x0130
117 device pci 1.0 on # PXB 2 0x0130
118 device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
119 device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
121 device pci 2.0 on end # PCI E 1 #0x0132
122 device pci 3.0 on end # PCI E 2
123 device pci 4.0 on end # PCI E 3
124 device pci 5.0 on end # PCI E 4
126 chip southbridge/broadcom/bcm5785 # HT1000
127 device pci 0.0 on # HT PXB 0x0036
128 device pci d.0 on end # PPBX 0x0104
129 device pci e.0 on end # SATA 0x024a
131 device pci 1.0 on # Legacy pci main 0x0205
132 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
133 device i2c 71 on end #0 pca9554 0
134 device i2c 71 on end #0 pca9554 1
135 device i2c 71 on end #0 pca9554 2
136 device i2c 71 on end #0 pca9554 3
137 device i2c 71 on end #0 pca9554 4
138 device i2c 71 on end #0 pca9554 5
139 device i2c 71 on #0 pca9554 6
140 chip drivers/generic/generic #dimm 0-0-0
143 chip drivers/generic/generic #dimm 0-0-1
146 chip drivers/generic/generic #dimm 0-1-0
149 chip drivers/generic/generic #dimm 0-1-1
153 device i2c 71 on #1 pca9554 7
154 chip drivers/generic/generic #dimm 1-0-0
157 chip drivers/generic/generic #dimm 1-0-1
160 chip drivers/generic/generic #dimm 1-1-0
163 chip drivers/generic/generic #dimm 1-1-1
170 device pci 1.1 on end # IDE 0x0214
171 device pci 1.2 on # LPC 0x0234
172 chip superio/nsc/pc87417
173 device pnp 2e.0 off # Floppy
178 device pnp 2e.1 off # Parallel Port
182 device pnp 2e.2 off # Com 2
186 device pnp 2e.3 on # Com 1
190 device pnp 2e.4 off end # SWC
191 device pnp 2e.5 off end # Mouse
192 device pnp 2e.6 on # Keyboard
197 device pnp 2e.7 off end # GPIO
198 device pnp 2e.f off end # XBUS
199 device pnp 2e.10 on #RTC
205 device pci 1.3 on end # WDTimer 0x0238
206 device pci 1.4 on end # XIOAPIC0 0x0235
207 device pci 1.5 on end # XIOAPIC1
208 device pci 1.6 on end # XIOAPIC2
209 device pci 2.0 on end # USB 0x0223
210 device pci 2.1 on end # USB
211 device pci 2.2 on end # USB
212 #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
213 chip drivers/pci/onboard
214 device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
215 # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
216 register "rom_address" = "0xfff80000"
219 #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
220 # chip drivers/pci/onboard
221 # device pci 0.0 on end # fake, will be disabled
223 # chip drivers/pci/onboard
224 # device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
225 # register "rom_address" = "0xfff80000"
229 end # device pci 18.0
231 device pci 18.0 on end
232 device pci 18.0 on end
233 device pci 18.1 on end
234 device pci 18.2 on end
235 device pci 18.3 on end
240 # chip drivers/generic/debug
241 # device pnp 0.0 off end # chip name
242 # device pnp 0.1 on end # pci_regs_all
243 # device pnp 0.2 off end # mem
244 # device pnp 0.3 off end # cpuid
245 # device pnp 0.4 off end # smbus_regs_all
246 # device pnp 0.5 off end # dual core msr
247 # device pnp 0.6 off end # cache size
248 # device pnp 0.7 off end # tsc