2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
26 #if CONFIG_LOGICAL_CPUS==1
27 #include <cpu/amd/multicore.h>
29 #include <cpu/amd/amdfam10_sysconf.h>
30 #if CONFIG_AMD_SB_CIMX
34 /* Global variables for MB layouts and these will be shared by irqtable mptable
35 * and acpi_tables busnum is default.
43 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
44 * You may need to preset pci1234 for HTIO board,
45 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
52 * HT Chain device num, actually it is unit id base of every ht device in chain,
53 * assume every chain only have 4 ht device at most
64 extern void get_pci1234(void);
66 static u32 get_bus_conf_done = 0;
68 void get_bus_conf(void)
74 if (get_bus_conf_done == 1)
75 return; /* do it only once */
76 get_bus_conf_done = 1;
78 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
79 for (i = 0; i < sysconf.hc_possible_num; i++) {
80 sysconf.pci1234[i] = pci1234x[i];
81 sysconf.hcdn[i] = hcdnx[i];
86 sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
87 sbdn_rs780 = sysconf.sbdn;
90 for (i = 0; i < 3; i++) {
93 for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
97 for (i = 0; i < 256; i++) {
98 bus_type[i] = 0; /* default ISA bus. */
101 bus_type[0] = 1; /* pci */
103 bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
104 bus_sb800[0] = bus_rs780[0];
106 bus_type[bus_rs780[0]] = 1;
109 dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
111 bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
112 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
114 for (j = bus_sb800[1]; j < bus_isa; j++)
118 for (i = 0; i < 4; i++) {
119 dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i));
121 bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
122 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
126 for (j = bus_sb800[2]; j < bus_isa; j++)
130 for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
131 dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
133 bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
134 if(255 != bus_rs780[i]) {
135 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
137 bus_type[bus_rs780[i]] = 1; /* PCI bus. */
142 /* I/O APICs: APIC ID Version State Address */
144 #if CONFIG_LOGICAL_CPUS==1
145 apicid_base = get_apicid_base(1);
147 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
149 apicid_sb800 = apicid_base + 0;
151 #if CONFIG_AMD_SB_CIMX