sigh

diff --git a/src/mainboard/asus/m5a99x-evo/fadt.c b/src/mainboard/asus/m5a99x-evo/fadt.c
index adba78055bad02ca80e5bfe04891449147ef3ec0..420c3bac8ad12341e2daa035dd6417429d7056ff 100644 (file)
--- a/src/mainboard/asus/m5a99x-evo/fadt.c
+++ b/src/mainboard/asus/m5a99x-evo/fadt.c
@@ -26,7 +26,7 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
-#include "SBPLATFORM.h"
+#include "SbPlatform.h"
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

diff --git a/src/mainboard/asus/m5a99x-evo/get_bus_conf.c b/src/mainboard/asus/m5a99x-evo/get_bus_conf.c
index 5c21e09d53a99bdd4823440dee13052176b69255..4a939dc9394f7a308730001041494cc438f56d63 100644 (file)
--- a/src/mainboard/asus/m5a99x-evo/get_bus_conf.c
+++ b/src/mainboard/asus/m5a99x-evo/get_bus_conf.c
@@ -28,7 +28,7 @@
 #endif
 #include <cpu/amd/amdfam10_sysconf.h>
 #if CONFIG_AMD_SB_CIMX
-#include <sb_cimx.h>
+#include <SbEarly.h>
 #endif
 
 /* Global variables for MB layouts and these will be shared by irqtable mptable

diff --git a/src/mainboard/asus/m5a99x-evo/mainboard.c b/src/mainboard/asus/m5a99x-evo/mainboard.c
index d6c3a5b615c25dcd2b15da212437cbbcfd038e95..b4bc11aca8f2a119f89e9ca0fe1394591cd7931d 100644 (file)
--- a/src/mainboard/asus/m5a99x-evo/mainboard.c
+++ b/src/mainboard/asus/m5a99x-evo/mainboard.c
@@ -25,7 +25,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-#include "SBPLATFORM.h"
+#include "SbPlatform.h"
 #include "chip.h"
 
 uint64_t uma_memory_base, uma_memory_size;

diff --git a/src/mainboard/asus/m5a99x-evo/mptable.c b/src/mainboard/asus/m5a99x-evo/mptable.c
index 516b915c45912d46fa921b83be1da5ee32032595..4396a2b6b38a425ca394c810b981a36e2d320f7d 100644 (file)
--- a/src/mainboard/asus/m5a99x-evo/mptable.c
+++ b/src/mainboard/asus/m5a99x-evo/mptable.c
@@ -24,7 +24,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>
-#include <SBPLATFORM.h>
+#include <SbPlatform.h>
 
 extern int bus_isa;
 extern u8 bus_rs780[11];

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 89bd6733ce26e85821901981f28a17976b7b820e..018b6c83b0d8e81dc3be08340885918f266e1b5b 100644 (file)
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -47,8 +47,10 @@
 #endif
 
 #include <cpu/amd/amdfam10_sysconf.h>
-#if CONFIG_AMD_SB_CIMX
+#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800
 #include <sb_cimx.h>
+#elif CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
+#include <SbEarly.h>
 #endif
 
 struct amdfam10_sysconf_t sysconf;
@@ -1448,7 +1450,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 static void cpu_bus_init(device_t dev)
 {
        initialize_cpus(dev->link_list);
-#if CONFIG_AMD_SB_CIMX
+#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 || CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
        sb_After_Pci_Init();
        sb_Mid_Post_Init();
 #endif

diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 9d49a52d545b9fa32cf5d610fe6b622890feb8a6..3f4020f0c0cf563ccfbca5d8ecf930f0693276dc 100644 (file)
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -23,8 +23,8 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>           /* inl, outl */
 #include <arch/romcc_io.h>     /* device_t */
-#include "SBPLATFORM.h"
-#include "sb_cimx.h"
+#include "SbPlatform.h"
+#include "SbEarly.h"
 #include "cfg.h"               /*sb800_cimx_config*/
 
 

diff --git a/src/vendorcode/amd/cimx/sb900/GppHp.c b/src/vendorcode/amd/cimx/sb900/GppHp.c
index 4975b8ab4e5142663175600b5c62557d5da7aac8..59e2e4dd70c8ffaf735ce5bf324f2bbf607a2cef 100755 (executable)
--- a/src/vendorcode/amd/cimx/sb900/GppHp.c
+++ b/src/vendorcode/amd/cimx/sb900/GppHp.c
@@ -51,7 +51,13 @@ VOID  sbGppDynamicPowerSaving (IN AMDSBCFG* pConfig );
 VOID  sbGppForceGen1 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
 VOID  sbGppForceGen2 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
 UINT8 GppPortPollingLtssm (IN AMDSBCFG* pConfig, IN UINT8 ActivePorts, IN BOOLEAN IsGen2);
+VOID SbStall (IN UINT32 uSec);
+VOID outPort80 (IN UINT32 pcode);
 
+// wtf Declaration ...
+VOID sbGppHotPlugSmiProcess (IN AMDSBCFG* pConfig, IN UINT32 HpPort);
+VOID sbGppHotUnplugSmiProcess (IN AMDSBCFG* pConfig, IN UINT32 HpPort);
+VOID sbGppHotplugSmiCallback (IN AMDSBCFG* pConfig, IN BOOLEAN IsPlugged);
 
 /**
  * GPP hot plug handler
@@ -61,8 +67,8 @@ UINT8 GppPortPollingLtssm (IN AMDSBCFG* pConfig, IN UINT8 ActivePorts, IN BOOLEA
  * @param[in] HpPort    The hot plug port number.
  *
  */
-VOID
-sbGppHotPlugSmiProcess (
+
+VOID sbGppHotPlugSmiProcess (
   IN       AMDSBCFG*     pConfig,
   IN       UINT32        HpPort
   )