src/mainboard/asus/m5a99x-evo/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* DefinitionBlock Statement */
  21 DefinitionBlock (
  22         "DSDT.AML",           /* Output filename */
  23         "DSDT",                 /* Signature */
  24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  25         "ASUS    ",               /* OEMID */
  26         "M5A99   ",          /* TABLE ID */
  27         0x00010001      /* OEM Revision */
  28         )
  29 {       /* Start of ASL file */
  30         /* #include "../../../arch/x86/acpi/debug.asl" */               /* Include global debug methods if needed */
  31
  32         /* Data to be patched by the BIOS during POST */
  33         /* FIXME the patching is not done yet! */
  34         /* Memory related values */
  35         Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
  36         Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
  37         Name(PBLN, 0x0) /* Length of BIOS area */
  38
  39         Name(PCBA, 0xE0000000)  /* Base address of PCIe config space */
  40         Name(HPBA, 0xFED00000)  /* Base address of HPET table */
  41
  42         Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
  43
  44         /* USB overcurrent mapping pins.   */
  45         Name(UOM0, 0)
  46         Name(UOM1, 2)
  47         Name(UOM2, 0)
  48         Name(UOM3, 7)
  49         Name(UOM4, 2)
  50         Name(UOM5, 2)
  51         Name(UOM6, 6)
  52         Name(UOM7, 2)
  53         Name(UOM8, 6)
  54         Name(UOM9, 6)
  55
  56         /* Some global data */
  57         Name(OSTP, 3)           /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
  58         Name(OSV, Ones) /* Assume nothing */
  59         Name(PMOD, One) /* Assume APIC */
  60
  61         /*
  62          * Processor Object
  63          *
  64          */
  65         Scope (\_PR) {          /* define processor scope */
  66                 Processor(
  67                         CPU0,           /* name space name */
  68                         0,              /* Unique number for this processor */
  69                         0x808,          /* PBLK system I/O address !hardcoded! */
  70                         0x06            /* PBLKLEN for boot processor */
  71                         ) {
  72                         #include "acpi/cpstate.asl"
  73                 }
  74
  75                 Processor(
  76                         CPU1,           /* name space name */
  77                         1,              /* Unique number for this processor */
  78                         0x0000,         /* PBLK system I/O address !hardcoded! */
  79                         0x00            /* PBLKLEN for boot processor */
  80                         ) {
  81                         #include "acpi/cpstate.asl"
  82                 }
  83
  84                 Processor(
  85                         CPU2,           /* name space name */
  86                         2,              /* Unique number for this processor */
  87                         0x0000,         /* PBLK system I/O address !hardcoded! */
  88                         0x00            /* PBLKLEN for boot processor */
  89                         ) {
  90                         #include "acpi/cpstate.asl"
  91                 }
  92
  93                 Processor(
  94                         CPU3,           /* name space name */
  95                         3,              /* Unique number for this processor */
  96                         0x0000,         /* PBLK system I/O address !hardcoded! */
  97                         0x00            /* PBLKLEN for boot processor */
  98                         ) {
  99                         #include "acpi/cpstate.asl"
 100                 }
 101
 102                 Processor(
 103                         CPU4,           /* name space name */
 104                         4,              /* Unique number for this processor */
 105                         0x0000,         /* PBLK system I/O address !hardcoded! */
 106                         0x00            /* PBLKLEN for boot processor */
 107                         ) {
 108                         #include "acpi/cpstate.asl"
 109                 }
 110
 111                 Processor(
 112                         CPU5,           /* name space name */
 113                         5,              /* Unique number for this processor */
 114                         0x0000,         /* PBLK system I/O address !hardcoded! */
 115                         0x00            /* PBLKLEN for boot processor */
 116                         ) {
 117                         #include "acpi/cpstate.asl"
 118                 }
 119         } /* End _PR scope */
 120
 121         /* PIC IRQ mapping registers, C00h-C01h. */
 122         OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
 123                 Field(PRQM, ByteAcc, NoLock, Preserve) {
 124                 PRQI, 0x00000008,
 125                 PRQD, 0x00000008,  /* Offset: 1h */
 126         }
 127         IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 128                 PIRA, 0x00000008,       /* Index 0 */
 129                 PIRB, 0x00000008,       /* Index 1 */
 130                 PIRC, 0x00000008,       /* Index 2 */
 131                 PIRD, 0x00000008,       /* Index 3 */
 132                 PIRE, 0x00000008,       /* Index 4 */
 133                 PIRF, 0x00000008,       /* Index 5 */
 134                 PIRG, 0x00000008,       /* Index 6 */
 135                 PIRH, 0x00000008,       /* Index 7 */
 136         }
 137
 138         /* PCI Error control register */
 139         OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
 140                 Field(PERC, ByteAcc, NoLock, Preserve) {
 141                 SENS, 0x00000001,
 142                 PENS, 0x00000001,
 143                 SENE, 0x00000001,
 144                 PENE, 0x00000001,
 145         }
 146
 147         /* Client Management index/data registers */
 148         OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
 149                 Field(CMT, ByteAcc, NoLock, Preserve) {
 150                 CMTI,      8,
 151                 /* Client Management Data register */
 152                 G64E,   1,
 153                 G64O,      1,
 154                 G32O,      2,
 155                 ,       2,
 156                 GPSL,     2,
 157         }
 158
 159         /* GPM Port register */
 160         OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
 161                 Field(GPT, ByteAcc, NoLock, Preserve) {
 162                 GPB0,1,
 163                 GPB1,1,
 164                 GPB2,1,
 165                 GPB3,1,
 166                 GPB4,1,
 167                 GPB5,1,
 168                 GPB6,1,
 169                 GPB7,1,
 170         }
 171
 172         /* Flash ROM program enable register */
 173         OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
 174                 Field(FRE, ByteAcc, NoLock, Preserve) {
 175                 ,     0x00000006,
 176                 FLRE, 0x00000001,
 177         }
 178
 179         /* PM2 index/data registers */
 180         OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
 181                 Field(PM2R, ByteAcc, NoLock, Preserve) {
 182                 PM2I, 0x00000008,
 183                 PM2D, 0x00000008,
 184         }
 185
 186         /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
 187         OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
 188                 Field(PIOR, ByteAcc, NoLock, Preserve) {
 189                 PIOI, 0x00000008,
 190                 PIOD, 0x00000008,
 191         }
 192         IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 193                 Offset(0x00),   /* MiscControl */
 194                 , 1,
 195                 T1EE, 1,
 196                 T2EE, 1,
 197                 Offset(0x01),   /* MiscStatus */
 198                 , 1,
 199                 T1E, 1,
 200                 T2E, 1,
 201                 Offset(0x04),   /* SmiWakeUpEventEnable3 */
 202                 , 7,
 203                 SSEN, 1,
 204                 Offset(0x07),   /* SmiWakeUpEventStatus3 */
 205                 , 7,
 206                 CSSM, 1,
 207                 Offset(0x10),   /* AcpiEnable */
 208                 , 6,
 209                 PWDE, 1,
 210                 Offset(0x1C),   /* ProgramIoEnable */
 211                 , 3,
 212                 MKME, 1,
 213                 IO3E, 1,
 214                 IO2E, 1,
 215                 IO1E, 1,
 216                 IO0E, 1,
 217                 Offset(0x1D),   /* IOMonitorStatus */
 218                 , 3,
 219                 MKMS, 1,
 220                 IO3S, 1,
 221                 IO2S, 1,
 222                 IO1S, 1,
 223                 IO0S,1,
 224                 Offset(0x20),   /* AcpiPmEvtBlk. TODO: should be 0x60 */
 225                 APEB, 16,
 226                 Offset(0x36),   /* GEvtLevelConfig */
 227                 , 6,
 228                 ELC6, 1,
 229                 ELC7, 1,
 230                 Offset(0x37),   /* GPMLevelConfig0 */
 231                 , 3,
 232                 PLC0, 1,
 233                 PLC1, 1,
 234                 PLC2, 1,
 235                 PLC3, 1,
 236                 PLC8, 1,
 237                 Offset(0x38),   /* GPMLevelConfig1 */
 238                 , 1,
 239                  PLC4, 1,
 240                  PLC5, 1,
 241                 , 1,
 242                  PLC6, 1,
 243                  PLC7, 1,
 244                 Offset(0x3B),   /* PMEStatus1 */
 245                 GP0S, 1,
 246                 GM4S, 1,
 247                 GM5S, 1,
 248                 APS, 1,
 249                 GM6S, 1,
 250                 GM7S, 1,
 251                 GP2S, 1,
 252                 STSS, 1,
 253                 Offset(0x55),   /* SoftPciRst */
 254                 SPRE, 1,
 255                 , 1,
 256                 , 1,
 257                 PNAT, 1,
 258                 PWMK, 1,
 259                 PWNS, 1,
 260
 261                 /*      Offset(0x61), */        /*  Options_1 */
 262                 /*              ,7,  */
 263                 /*              R617,1, */
 264
 265                 Offset(0x65),   /* UsbPMControl */
 266                 , 4,
 267                 URRE, 1,
 268                 Offset(0x68),   /* MiscEnable68 */
 269                 , 3,
 270                 TMTE, 1,
 271                 , 1,
 272                 Offset(0x92),   /* GEVENTIN */
 273                 , 7,
 274                 E7IS, 1,
 275                 Offset(0x96),   /* GPM98IN */
 276                 G8IS, 1,
 277                 G9IS, 1,
 278                 Offset(0x9A),   /* EnhanceControl */
 279                 ,7,
 280                 HPDE, 1,
 281                 Offset(0xA8),   /* PIO7654Enable */
 282                 IO4E, 1,
 283                 IO5E, 1,
 284                 IO6E, 1,
 285                 IO7E, 1,
 286                 Offset(0xA9),   /* PIO7654Status */
 287                 IO4S, 1,
 288                 IO5S, 1,
 289                 IO6S, 1,
 290                 IO7S, 1,
 291         }
 292
 293         /* PM1 Event Block
 294         * First word is PM1_Status, Second word is PM1_Enable
 295         */
 296         OperationRegion(P1EB, SystemIO, APEB, 0x04)
 297                 Field(P1EB, ByteAcc, NoLock, Preserve) {
 298                 TMST, 1,
 299                 ,    3,
 300                 BMST,    1,
 301                 GBST,   1,
 302                 Offset(0x01),
 303                 PBST, 1,
 304                 , 1,
 305                 RTST, 1,
 306                 , 3,
 307                 PWST, 1,
 308                 SPWS, 1,
 309                 Offset(0x02),
 310                 TMEN, 1,
 311                 , 4,
 312                 GBEN, 1,
 313                 Offset(0x03),
 314                 PBEN, 1,
 315                 , 1,
 316                 RTEN, 1,
 317                 , 3,
 318                 PWDA, 1,
 319         }
 320
 321         Scope(\_SB) {
 322                 /* PCIe Configuration Space for 16 busses */
 323                 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
 324                         Field(PCFG, ByteAcc, NoLock, Preserve) {
 325                         /* Byte offsets are computed using the following technique:
 326                          * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 327                          * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 328                         */
 329                         Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
 330                         STB5, 32,
 331                         Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 332                         PT0D, 1,
 333                         PT1D, 1,
 334                         PT2D, 1,
 335                         PT3D, 1,
 336                         PT4D, 1,
 337                         PT5D, 1,
 338                         PT6D, 1,
 339                         PT7D, 1,
 340                         PT8D, 1,
 341                         PT9D, 1,
 342                         Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
 343                         SBIE, 1,
 344                         SBME, 1,
 345                         Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
 346                         SBRI, 8,
 347                         Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
 348                         SBB1, 32,
 349                         Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
 350                         ,14,
 351                         P92E, 1,                /* Port92 decode enable */
 352                 }
 353
 354                 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
 355                         Field(SB5, AnyAcc, NoLock, Preserve){
 356                         /* Port 0 */
 357                         Offset(0x120),          /* Port 0 Task file status */
 358                         P0ER, 1,
 359                         , 2,
 360                         P0DQ, 1,
 361                         , 3,
 362                         P0BY, 1,
 363                         Offset(0x128),          /* Port 0 Serial ATA status */
 364                         P0DD, 4,
 365                         , 4,
 366                         P0IS, 4,
 367                         Offset(0x12C),          /* Port 0 Serial ATA control */
 368                         P0DI, 4,
 369                         Offset(0x130),          /* Port 0 Serial ATA error */
 370                         , 16,
 371                         P0PR, 1,
 372
 373                         /* Port 1 */
 374                         offset(0x1A0),          /* Port 1 Task file status */
 375                         P1ER, 1,
 376                         , 2,
 377                         P1DQ, 1,
 378                         , 3,
 379                         P1BY, 1,
 380                         Offset(0x1A8),          /* Port 1 Serial ATA status */
 381                         P1DD, 4,
 382                         , 4,
 383                         P1IS, 4,
 384                         Offset(0x1AC),          /* Port 1 Serial ATA control */
 385                         P1DI, 4,
 386                         Offset(0x1B0),          /* Port 1 Serial ATA error */
 387                         , 16,
 388                         P1PR, 1,
 389
 390                         /* Port 2 */
 391                         Offset(0x220),          /* Port 2 Task file status */
 392                         P2ER, 1,
 393                         , 2,
 394                         P2DQ, 1,
 395                         , 3,
 396                         P2BY, 1,
 397                         Offset(0x228),          /* Port 2 Serial ATA status */
 398                         P2DD, 4,
 399                         , 4,
 400                         P2IS, 4,
 401                         Offset(0x22C),          /* Port 2 Serial ATA control */
 402                         P2DI, 4,
 403                         Offset(0x230),          /* Port 2 Serial ATA error */
 404                         , 16,
 405                         P2PR, 1,
 406
 407                         /* Port 3 */
 408                         Offset(0x2A0),          /* Port 3 Task file status */
 409                         P3ER, 1,
 410                         , 2,
 411                         P3DQ, 1,
 412                         , 3,
 413                         P3BY, 1,
 414                         Offset(0x2A8),          /* Port 3 Serial ATA status */
 415                         P3DD, 4,
 416                         , 4,
 417                         P3IS, 4,
 418                         Offset(0x2AC),          /* Port 3 Serial ATA control */
 419                         P3DI, 4,
 420                         Offset(0x2B0),          /* Port 3 Serial ATA error */
 421                         , 16,
 422                         P3PR, 1,
 423                 }
 424         }
 425
 426
 427         #include "acpi/routing.asl"
 428
 429         Scope(\_SB) {
 430
 431                 Method(CkOT, 0){
 432
 433                         if(LNotEqual(OSTP, Ones)) {Return(OSTP)}        /* OS version was already detected */
 434
 435                         if(CondRefOf(\_OSI,Local1))
 436                         {
 437                                 Store(1, OSTP)                /* Assume some form of XP */
 438                                 if (\_OSI("Windows 2006"))      /* Vista */
 439                                 {
 440                                         Store(2, OSTP)
 441                                 }
 442                         } else {
 443                                 If(WCMP(\_OS,"Linux")) {
 444                                         Store(3, OSTP)            /* Linux */
 445                                 } Else {
 446                                         Store(4, OSTP)            /* Gotta be WinCE */
 447                                 }
 448                         }
 449                         Return(OSTP)
 450                 }
 451
 452                 Method(_PIC, 0x01, NotSerialized)
 453                 {
 454                         If (Arg0)
 455                         {
 456                                 \_SB.CIRQ()
 457                         }
 458                         Store(Arg0, PMOD)
 459                 }
 460                 Method(CIRQ, 0x00, NotSerialized){
 461                         Store(0, PIRA)
 462                         Store(0, PIRB)
 463                         Store(0, PIRC)
 464                         Store(0, PIRD)
 465                         Store(0, PIRE)
 466                         Store(0, PIRF)
 467                         Store(0, PIRG)
 468                         Store(0, PIRH)
 469                 }
 470
 471                 Name(IRQB, ResourceTemplate(){
 472                         IRQ(Level,ActiveLow,Shared){15}
 473                 })
 474
 475                 Name(IRQP, ResourceTemplate(){
 476                         IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
 477                 })
 478
 479                 Name(PITF, ResourceTemplate(){
 480                         IRQ(Level,ActiveLow,Exclusive){9}
 481                 })
 482
 483                 Device(INTA) {
 484                         Name(_HID, EISAID("PNP0C0F"))
 485                         Name(_UID, 1)
 486
 487                         Method(_STA, 0) {
 488                                 if (PIRA) {
 489                                         Return(0x0B) /* sata is invisible */
 490                                 } else {
 491                                         Return(0x09) /* sata is disabled */
 492                                 }
 493                         } /* End Method(_SB.INTA._STA) */
 494
 495                         Method(_DIS ,0) {
 496                                 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
 497                                 Store(0, PIRA)
 498                         } /* End Method(_SB.INTA._DIS) */
 499
 500                         Method(_PRS ,0) {
 501                                 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
 502                                 Return(IRQP)
 503                         } /* Method(_SB.INTA._PRS) */
 504
 505                         Method(_CRS ,0) {
 506                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 507                                 CreateWordField(IRQB, 0x1, IRQN)
 508                                 ShiftLeft(1, PIRA, IRQN)
 509                                 Return(IRQB)
 510                         } /* Method(_SB.INTA._CRS) */
 511
 512                         Method(_SRS, 1) {
 513                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 514                                 CreateWordField(ARG0, 1, IRQM)
 515
 516                                 /* Use lowest available IRQ */
 517                                 FindSetRightBit(IRQM, Local0)
 518                                 if (Local0) {
 519                                         Decrement(Local0)
 520                                 }
 521                                 Store(Local0, PIRA)
 522                         } /* End Method(_SB.INTA._SRS) */
 523                 } /* End Device(INTA) */
 524
 525                 Device(INTB) {
 526                         Name(_HID, EISAID("PNP0C0F"))
 527                         Name(_UID, 2)
 528
 529                         Method(_STA, 0) {
 530                                 if (PIRB) {
 531                                         Return(0x0B) /* sata is invisible */
 532                                 } else {
 533                                         Return(0x09) /* sata is disabled */
 534                                 }
 535                         } /* End Method(_SB.INTB._STA) */
 536
 537                         Method(_DIS ,0) {
 538                                 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
 539                                 Store(0, PIRB)
 540                         } /* End Method(_SB.INTB._DIS) */
 541
 542                         Method(_PRS ,0) {
 543                                 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
 544                                 Return(IRQP)
 545                         } /* Method(_SB.INTB._PRS) */
 546
 547                         Method(_CRS ,0) {
 548                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 549                                 CreateWordField(IRQB, 0x1, IRQN)
 550                                 ShiftLeft(1, PIRB, IRQN)
 551                                 Return(IRQB)
 552                         } /* Method(_SB.INTB._CRS) */
 553
 554                         Method(_SRS, 1) {
 555                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 556                                 CreateWordField(ARG0, 1, IRQM)
 557
 558                                 /* Use lowest available IRQ */
 559                                 FindSetRightBit(IRQM, Local0)
 560                                 if (Local0) {
 561                                         Decrement(Local0)
 562                                 }
 563                                 Store(Local0, PIRB)
 564                         } /* End Method(_SB.INTB._SRS) */
 565                 } /* End Device(INTB)  */
 566
 567                 Device(INTC) {
 568                         Name(_HID, EISAID("PNP0C0F"))
 569                         Name(_UID, 3)
 570
 571                         Method(_STA, 0) {
 572                                 if (PIRC) {
 573                                         Return(0x0B) /* sata is invisible */
 574                                 } else {
 575                                         Return(0x09) /* sata is disabled */
 576                                 }
 577                         } /* End Method(_SB.INTC._STA) */
 578
 579                         Method(_DIS ,0) {
 580                                 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
 581                                 Store(0, PIRC)
 582                         } /* End Method(_SB.INTC._DIS) */
 583
 584                         Method(_PRS ,0) {
 585                                 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
 586                                 Return(IRQP)
 587                         } /* Method(_SB.INTC._PRS) */
 588
 589                         Method(_CRS ,0) {
 590                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 591                                 CreateWordField(IRQB, 0x1, IRQN)
 592                                 ShiftLeft(1, PIRC, IRQN)
 593                                 Return(IRQB)
 594                         } /* Method(_SB.INTC._CRS) */
 595
 596                         Method(_SRS, 1) {
 597                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 598                                 CreateWordField(ARG0, 1, IRQM)
 599
 600                                 /* Use lowest available IRQ */
 601                                 FindSetRightBit(IRQM, Local0)
 602                                 if (Local0) {
 603                                         Decrement(Local0)
 604                                 }
 605                                 Store(Local0, PIRC)
 606                         } /* End Method(_SB.INTC._SRS) */
 607                 } /* End Device(INTC)  */
 608
 609                 Device(INTD) {
 610                         Name(_HID, EISAID("PNP0C0F"))
 611                         Name(_UID, 4)
 612
 613                         Method(_STA, 0) {
 614                                 if (PIRD) {
 615                                         Return(0x0B) /* sata is invisible */
 616                                 } else {
 617                                         Return(0x09) /* sata is disabled */
 618                                 }
 619                         } /* End Method(_SB.INTD._STA) */
 620
 621                         Method(_DIS ,0) {
 622                                 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
 623                                 Store(0, PIRD)
 624                         } /* End Method(_SB.INTD._DIS) */
 625
 626                         Method(_PRS ,0) {
 627                                 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
 628                                 Return(IRQP)
 629                         } /* Method(_SB.INTD._PRS) */
 630
 631                         Method(_CRS ,0) {
 632                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 633                                 CreateWordField(IRQB, 0x1, IRQN)
 634                                 ShiftLeft(1, PIRD, IRQN)
 635                                 Return(IRQB)
 636                         } /* Method(_SB.INTD._CRS) */
 637
 638                         Method(_SRS, 1) {
 639                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 640                                 CreateWordField(ARG0, 1, IRQM)
 641
 642                                 /* Use lowest available IRQ */
 643                                 FindSetRightBit(IRQM, Local0)
 644                                 if (Local0) {
 645                                         Decrement(Local0)
 646                                 }
 647                                 Store(Local0, PIRD)
 648                         } /* End Method(_SB.INTD._SRS) */
 649                 } /* End Device(INTD)  */
 650
 651                 Device(INTE) {
 652                         Name(_HID, EISAID("PNP0C0F"))
 653                         Name(_UID, 5)
 654
 655                         Method(_STA, 0) {
 656                                 if (PIRE) {
 657                                         Return(0x0B) /* sata is invisible */
 658                                 } else {
 659                                         Return(0x09) /* sata is disabled */
 660                                 }
 661                         } /* End Method(_SB.INTE._STA) */
 662
 663                         Method(_DIS ,0) {
 664                                 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
 665                                 Store(0, PIRE)
 666                         } /* End Method(_SB.INTE._DIS) */
 667
 668                         Method(_PRS ,0) {
 669                                 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
 670                                 Return(IRQP)
 671                         } /* Method(_SB.INTE._PRS) */
 672
 673                         Method(_CRS ,0) {
 674                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 675                                 CreateWordField(IRQB, 0x1, IRQN)
 676                                 ShiftLeft(1, PIRE, IRQN)
 677                                 Return(IRQB)
 678                         } /* Method(_SB.INTE._CRS) */
 679
 680                         Method(_SRS, 1) {
 681                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 682                                 CreateWordField(ARG0, 1, IRQM)
 683
 684                                 /* Use lowest available IRQ */
 685                                 FindSetRightBit(IRQM, Local0)
 686                                 if (Local0) {
 687                                         Decrement(Local0)
 688                                 }
 689                                 Store(Local0, PIRE)
 690                         } /* End Method(_SB.INTE._SRS) */
 691                 } /* End Device(INTE)  */
 692
 693                 Device(INTF) {
 694                         Name(_HID, EISAID("PNP0C0F"))
 695                         Name(_UID, 6)
 696
 697                         Method(_STA, 0) {
 698                                 if (PIRF) {
 699                                         Return(0x0B) /* sata is invisible */
 700                                 } else {
 701                                         Return(0x09) /* sata is disabled */
 702                                 }
 703                         } /* End Method(_SB.INTF._STA) */
 704
 705                         Method(_DIS ,0) {
 706                                 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
 707                                 Store(0, PIRF)
 708                         } /* End Method(_SB.INTF._DIS) */
 709
 710                         Method(_PRS ,0) {
 711                                 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
 712                                 Return(PITF)
 713                         } /* Method(_SB.INTF._PRS) */
 714
 715                         Method(_CRS ,0) {
 716                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 717                                 CreateWordField(IRQB, 0x1, IRQN)
 718                                 ShiftLeft(1, PIRF, IRQN)
 719                                 Return(IRQB)
 720                         } /* Method(_SB.INTF._CRS) */
 721
 722                         Method(_SRS, 1) {
 723                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 724                                 CreateWordField(ARG0, 1, IRQM)
 725
 726                                 /* Use lowest available IRQ */
 727                                 FindSetRightBit(IRQM, Local0)
 728                                 if (Local0) {
 729                                         Decrement(Local0)
 730                                 }
 731                                 Store(Local0, PIRF)
 732                         } /*  End Method(_SB.INTF._SRS) */
 733                 } /* End Device(INTF)  */
 734
 735                 Device(INTG) {
 736                         Name(_HID, EISAID("PNP0C0F"))
 737                         Name(_UID, 7)
 738
 739                         Method(_STA, 0) {
 740                                 if (PIRG) {
 741                                         Return(0x0B) /* sata is invisible */
 742                                 } else {
 743                                         Return(0x09) /* sata is disabled */
 744                                 }
 745                         } /* End Method(_SB.INTG._STA)  */
 746
 747                         Method(_DIS ,0) {
 748                                 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
 749                                 Store(0, PIRG)
 750                         } /* End Method(_SB.INTG._DIS)  */
 751
 752                         Method(_PRS ,0) {
 753                                 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
 754                                 Return(IRQP)
 755                         } /* Method(_SB.INTG._CRS)  */
 756
 757                         Method(_CRS ,0) {
 758                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 759                                 CreateWordField(IRQB, 0x1, IRQN)
 760                                 ShiftLeft(1, PIRG, IRQN)
 761                                 Return(IRQB)
 762                         } /* Method(_SB.INTG._CRS)  */
 763
 764                         Method(_SRS, 1) {
 765                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 766                                 CreateWordField(ARG0, 1, IRQM)
 767
 768                                 /* Use lowest available IRQ */
 769                                 FindSetRightBit(IRQM, Local0)
 770                                 if (Local0) {
 771                                         Decrement(Local0)
 772                                 }
 773                                 Store(Local0, PIRG)
 774                         } /* End Method(_SB.INTG._SRS)  */
 775                 } /* End Device(INTG)  */
 776
 777                 Device(INTH) {
 778                         Name(_HID, EISAID("PNP0C0F"))
 779                         Name(_UID, 8)
 780
 781                         Method(_STA, 0) {
 782                                 if (PIRH) {
 783                                         Return(0x0B) /* sata is invisible */
 784                                 } else {
 785                                         Return(0x09) /* sata is disabled */
 786                                 }
 787                         } /* End Method(_SB.INTH._STA)  */
 788
 789                         Method(_DIS ,0) {
 790                                 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
 791                                 Store(0, PIRH)
 792                         } /* End Method(_SB.INTH._DIS)  */
 793
 794                         Method(_PRS ,0) {
 795                                 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
 796                                 Return(IRQP)
 797                         } /* Method(_SB.INTH._CRS)  */
 798
 799                         Method(_CRS ,0) {
 800                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 801                                 CreateWordField(IRQB, 0x1, IRQN)
 802                                 ShiftLeft(1, PIRH, IRQN)
 803                                 Return(IRQB)
 804                         } /* Method(_SB.INTH._CRS)  */
 805
 806                         Method(_SRS, 1) {
 807                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 808                                 CreateWordField(ARG0, 1, IRQM)
 809
 810                                 /* Use lowest available IRQ */
 811                                 FindSetRightBit(IRQM, Local0)
 812                                 if (Local0) {
 813                                         Decrement(Local0)
 814                                 }
 815                                 Store(Local0, PIRH)
 816                         } /* End Method(_SB.INTH._SRS)  */
 817                 } /* End Device(INTH)   */
 818
 819         }   /* End Scope(_SB)  */
 820
 821
 822         /* Supported sleep states: */
 823         Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
 824
 825         If (LAnd(SSFG, 0x01)) {
 826                 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
 827         }
 828         If (LAnd(SSFG, 0x02)) {
 829                 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
 830         }
 831         If (LAnd(SSFG, 0x04)) {
 832                 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
 833         }
 834         If (LAnd(SSFG, 0x08)) {
 835                 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
 836         }
 837
 838         Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
 839
 840         Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
 841         Name(CSMS, 0)                   /* Current System State */
 842
 843         /* Wake status package */
 844         Name(WKST,Package(){Zero, Zero})
 845
 846         /*
 847         * \_PTS - Prepare to Sleep method
 848         *
 849         *       Entry:
 850         *               Arg0=The value of the sleeping state S1=1, S2=2, etc
 851         *
 852         * Exit:
 853         *               -none-
 854         *
 855         * The _PTS control method is executed at the beginning of the sleep process
 856         * for S1-S5. The sleeping value is passed to the _PTS control method.   This
 857         * control method may be executed a relatively long time before entering the
 858         * sleep state and the OS may abort      the operation without notification to
 859         * the ACPI driver.  This method cannot modify the configuration or power
 860         * state of any device in the system.
 861         */
 862         Method(\_PTS, 1) {
 863                 /* DBGO("\\_PTS\n") */
 864                 /* DBGO("From S0 to S") */
 865                 /* DBGO(Arg0) */
 866                 /* DBGO("\n") */
 867
 868                 /* Don't allow PCIRST# to reset USB */
 869                 if (LEqual(Arg0,3)){
 870                         Store(0,URRE)
 871                 }
 872
 873                 /* Clear sleep SMI status flag and enable sleep SMI trap. */
 874                 /*Store(One, CSSM)
 875                 Store(One, SSEN)*/
 876
 877                 /* On older chips, clear PciExpWakeDisEn */
 878                 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
 879                 *       Store(0,\_SB.PWDE)
 880                 *}
 881                 */
 882
 883                 /* Clear wake status structure. */
 884                 Store(0, Index(WKST,0))
 885                 Store(0, Index(WKST,1))
 886         } /* End Method(\_PTS) */
 887
 888         /*
 889         *  The following method results in a "not a valid reserved NameSeg"
 890         *  warning so I have commented it out for the duration.  It isn't
 891         *  used, so it could be removed.
 892         *
 893         *
 894         *       \_GTS OEM Going To Sleep method
 895         *
 896         *       Entry:
 897         *               Arg0=The value of the sleeping state S1=1, S2=2
 898         *
 899         *       Exit:
 900         *               -none-
 901         *
 902         *  Method(\_GTS, 1) {
 903         *  DBGO("\\_GTS\n")
 904         *  DBGO("From S0 to S")
 905         *  DBGO(Arg0)
 906         *  DBGO("\n")
 907         *  }
 908         */
 909
 910         /*
 911         *       \_BFS OEM Back From Sleep method
 912         *
 913         *       Entry:
 914         *               Arg0=The value of the sleeping state S1=1, S2=2
 915         *
 916         *       Exit:
 917         *               -none-
 918         */
 919         Method(\_BFS, 1) {
 920                 /* DBGO("\\_BFS\n") */
 921                 /* DBGO("From S") */
 922                 /* DBGO(Arg0) */
 923                 /* DBGO(" to S0\n") */
 924         }
 925
 926         /*
 927         *  \_WAK System Wake method
 928         *
 929         *       Entry:
 930         *               Arg0=The value of the sleeping state S1=1, S2=2
 931         *
 932         *       Exit:
 933         *               Return package of 2 DWords
 934         *               Dword 1 - Status
 935         *                       0x00000000      wake succeeded
 936         *                       0x00000001      Wake was signaled but failed due to lack of power
 937         *                       0x00000002      Wake was signaled but failed due to thermal condition
 938         *               Dword 2 - Power Supply state
 939         *                       if non-zero the effective S-state the power supply entered
 940         */
 941         Method(\_WAK, 1) {
 942                 /* DBGO("\\_WAK\n") */
 943                 /* DBGO("From S") */
 944                 /* DBGO(Arg0) */
 945                 /* DBGO(" to S0\n") */
 946
 947                 /* Re-enable HPET */
 948                 Store(1,HPDE)
 949
 950                 /* Restore PCIRST# so it resets USB */
 951                 if (LEqual(Arg0,3)){
 952                         Store(1,URRE)
 953                 }
 954
 955                 /* Arbitrarily clear PciExpWakeStatus */
 956                 Store(PWST, PWST)
 957
 958                 /* if(DeRefOf(Index(WKST,0))) {
 959                 *       Store(0, Index(WKST,1))
 960                 * } else {
 961                 *       Store(Arg0, Index(WKST,1))
 962                 * }
 963                 */
 964                 Return(WKST)
 965         } /* End Method(\_WAK) */
 966
 967         Scope(\_GPE) {  /* Start Scope GPE */
 968                 /*  General event 0  */
 969                 /* Method(_L00) {
 970                 *       DBGO("\\_GPE\\_L00\n")
 971                 * }
 972                 */
 973
 974                 /*  General event 1  */
 975                 /* Method(_L01) {
 976                 *       DBGO("\\_GPE\\_L00\n")
 977                 * }
 978                 */
 979
 980                 /*  General event 2  */
 981                 /* Method(_L02) {
 982                 *       DBGO("\\_GPE\\_L00\n")
 983                 * }
 984                 */
 985
 986                 /*  General event 3  */
 987                 Method(_L03) {
 988                         /* DBGO("\\_GPE\\_L00\n") */
 989                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 990                 }
 991
 992                 /*  General event 4  */
 993                 /* Method(_L04) {
 994                 *       DBGO("\\_GPE\\_L00\n")
 995                 * }
 996                 */
 997
 998                 /*  General event 5  */
 999                 /* Method(_L05) {
1000                 *       DBGO("\\_GPE\\_L00\n")
1001                 * }
1002                 */
1003
1004                 /*  General event 6 - Used for GPM6, moved to USB.asl */
1005                 /* Method(_L06) {
1006                 *       DBGO("\\_GPE\\_L00\n")
1007                 * }
1008                 */
1009
1010                 /*  General event 7 - Used for GPM7, moved to USB.asl */
1011                 /* Method(_L07) {
1012                 *       DBGO("\\_GPE\\_L07\n")
1013                 * }
1014                 */
1015
1016                 /*  Legacy PM event  */
1017                 Method(_L08) {
1018                         /* DBGO("\\_GPE\\_L08\n") */
1019                 }
1020
1021                 /*  Temp warning (TWarn) event  */
1022                 Method(_L09) {
1023                         /* DBGO("\\_GPE\\_L09\n") */
1024                         /* Notify (\_TZ.TZ00, 0x80) */
1025                 }
1026
1027                 /*  Reserved  */
1028                 /* Method(_L0A) {
1029                 *       DBGO("\\_GPE\\_L0A\n")
1030                 * }
1031                 */
1032
1033                 /*  USB controller PME#  */
1034                 Method(_L0B) {
1035                         /* DBGO("\\_GPE\\_L0B\n") */
1036                         Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1037                         Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1038                         Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1039                         Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1040                         Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1041                         Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
1042                         Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1043                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1044                 }
1045
1046                 /*  AC97 controller PME#  */
1047                 /* Method(_L0C) {
1048                 *       DBGO("\\_GPE\\_L0C\n")
1049                 * }
1050                 */
1051
1052                 /*  OtherTherm PME#  */
1053                 /* Method(_L0D) {
1054                 *       DBGO("\\_GPE\\_L0D\n")
1055                 * }
1056                 */
1057
1058                 /*  GPM9 SCI event - Moved to USB.asl */
1059                 /* Method(_L0E) {
1060                 *       DBGO("\\_GPE\\_L0E\n")
1061                 * }
1062                 */
1063
1064                 /*  PCIe HotPlug event  */
1065                 /* Method(_L0F) {
1066                 *       DBGO("\\_GPE\\_L0F\n")
1067                 * }
1068                 */
1069
1070                 /*  ExtEvent0 SCI event  */
1071                 Method(_L10) {
1072                         /* DBGO("\\_GPE\\_L10\n") */
1073                 }
1074
1075
1076                 /*  ExtEvent1 SCI event  */
1077                 Method(_L11) {
1078                         /* DBGO("\\_GPE\\_L11\n") */
1079                 }
1080
1081                 /*  PCIe PME# event  */
1082                 /* Method(_L12) {
1083                 *       DBGO("\\_GPE\\_L12\n")
1084                 * }
1085                 */
1086
1087                 /*  GPM0 SCI event - Moved to USB.asl */
1088                 /* Method(_L13) {
1089                 *       DBGO("\\_GPE\\_L13\n")
1090                 * }
1091                 */
1092
1093                 /*  GPM1 SCI event - Moved to USB.asl */
1094                 /* Method(_L14) {
1095                 *       DBGO("\\_GPE\\_L14\n")
1096                 * }
1097                 */
1098
1099                 /*  GPM2 SCI event - Moved to USB.asl */
1100                 /* Method(_L15) {
1101                 *       DBGO("\\_GPE\\_L15\n")
1102                 * }
1103                 */
1104
1105                 /*  GPM3 SCI event - Moved to USB.asl */
1106                 /* Method(_L16) {
1107                 *       DBGO("\\_GPE\\_L16\n")
1108                 * }
1109                 */
1110
1111                 /*  GPM8 SCI event - Moved to USB.asl */
1112                 /* Method(_L17) {
1113                 *       DBGO("\\_GPE\\_L17\n")
1114                 * }
1115                 */
1116
1117                 /*  GPIO0 or GEvent8 event  */
1118                 Method(_L18) {
1119                         /* DBGO("\\_GPE\\_L18\n") */
1120                         Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1121                         Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1122                         Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1123                         Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1124                         Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1125                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1126                 }
1127
1128                 /*  GPM4 SCI event - Moved to USB.asl */
1129                 /* Method(_L19) {
1130                 *       DBGO("\\_GPE\\_L19\n")
1131                 * }
1132                 */
1133
1134                 /*  GPM5 SCI event - Moved to USB.asl */
1135                 /* Method(_L1A) {
1136                 *       DBGO("\\_GPE\\_L1A\n")
1137                 * }
1138                 */
1139
1140                 /*  Azalia SCI event  */
1141                 Method(_L1B) {
1142                         /* DBGO("\\_GPE\\_L1B\n") */
1143                         Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1144                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1145                 }
1146
1147                 /*  GPM6 SCI event - Reassigned to _L06 */
1148                 /* Method(_L1C) {
1149                 *       DBGO("\\_GPE\\_L1C\n")
1150                 * }
1151                 */
1152
1153                 /*  GPM7 SCI event - Reassigned to _L07 */
1154                 /* Method(_L1D) {
1155                 *       DBGO("\\_GPE\\_L1D\n")
1156                 * }
1157                 */
1158
1159                 /*  GPIO2 or GPIO66 SCI event  */
1160                 /* Method(_L1E) {
1161                 *       DBGO("\\_GPE\\_L1E\n")
1162                 * }
1163                 */
1164
1165                 /*  SATA SCI event - Moved to sata.asl */
1166                 /* Method(_L1F) {
1167                 *        DBGO("\\_GPE\\_L1F\n")
1168                 * }
1169                 */
1170
1171         }       /* End Scope GPE */
1172
1173         #include "acpi/usb.asl"
1174
1175         /* South Bridge */
1176         Scope(\_SB) { /* Start \_SB scope */
1177                 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1178
1179                 /*  _SB.PCI0 */
1180                 /* Note: Only need HID on Primary Bus */
1181                 Device(PCI0) {
1182                         External (TOM1)
1183                         External (TOM2)
1184                         Name(_HID, EISAID("PNP0A03"))
1185                         Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
1186                         Method(_BBN, 0) { /* Bus number = 0 */
1187                                 Return(0)
1188                         }
1189                         Method(_STA, 0) {
1190                                 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1191                                 Return(0x0B)     /* Status is visible */
1192                         }
1193
1194                         Method(_PRT,0) {
1195                                 If(PMOD){ Return(APR0) }   /* APIC mode */
1196                                 Return (PR0)                  /* PIC Mode */
1197                         } /* end _PRT */
1198
1199                         /* Describe the Northbridge devices */
1200                         Device(AMRT) {
1201                                 Name(_ADR, 0x00000000)
1202                         } /* end AMRT */
1203
1204                         /* The internal GFX bridge */
1205                         Device(AGPB) {
1206                                 Name(_ADR, 0x00010000)
1207                                 Name(_PRW, Package() {0x18, 4})
1208                                 Method(_PRT,0) {
1209                                         Return (APR1)
1210                                 }
1211                         }  /* end AGPB */
1212
1213                         /* The external GFX bridge */
1214                         Device(PBR2) {
1215                                 Name(_ADR, 0x00020000)
1216                                 Name(_PRW, Package() {0x18, 4})
1217                                 Method(_PRT,0) {
1218                                         If(PMOD){ Return(APS2) }   /* APIC mode */
1219                                         Return (PS2)                  /* PIC Mode */
1220                                 } /* end _PRT */
1221                         } /* end PBR2 */
1222
1223                         /* Dev3 is also an external GFX bridge, not used in Herring */
1224
1225                         Device(PBR4) {
1226                                 Name(_ADR, 0x00040000)
1227                                 Name(_PRW, Package() {0x18, 4})
1228                                 Method(_PRT,0) {
1229                                         If(PMOD){ Return(APS4) }   /* APIC mode */
1230                                         Return (PS4)                  /* PIC Mode */
1231                                 } /* end _PRT */
1232                         } /* end PBR4 */
1233
1234                         Device(PBR5) {
1235                                 Name(_ADR, 0x00050000)
1236                                 Name(_PRW, Package() {0x18, 4})
1237                                 Method(_PRT,0) {
1238                                         If(PMOD){ Return(APS5) }   /* APIC mode */
1239                                         Return (PS5)                  /* PIC Mode */
1240                                 } /* end _PRT */
1241                         } /* end PBR5 */
1242
1243                         Device(PBR6) {
1244                                 Name(_ADR, 0x00060000)
1245                                 Name(_PRW, Package() {0x18, 4})
1246                                 Method(_PRT,0) {
1247                                         If(PMOD){ Return(APS6) }   /* APIC mode */
1248                                         Return (PS6)                  /* PIC Mode */
1249                                 } /* end _PRT */
1250                         } /* end PBR6 */
1251
1252                         /* The onboard EtherNet chip */
1253                         Device(PBR7) {
1254                                 Name(_ADR, 0x00070000)
1255                                 Name(_PRW, Package() {0x18, 4})
1256                                 Method(_PRT,0) {
1257                                         If(PMOD){ Return(APS7) }   /* APIC mode */
1258                                         Return (PS7)                  /* PIC Mode */
1259                                 } /* end _PRT */
1260                         } /* end PBR7 */
1261
1262                         /* GPP */
1263                         Device(PBR9) {
1264                                 Name(_ADR, 0x00090000)
1265                                 Name(_PRW, Package() {0x18, 4})
1266                                 Method(_PRT,0) {
1267                                         If(PMOD){ Return(APS9) }   /* APIC mode */
1268                                         Return (PS9)                  /* PIC Mode */
1269                                 } /* end _PRT */
1270                         } /* end PBR9 */
1271
1272                         Device(PBRa) {
1273                                 Name(_ADR, 0x000A0000)
1274                                 Name(_PRW, Package() {0x18, 4})
1275                                 Method(_PRT,0) {
1276                                         If(PMOD){ Return(APSa) }   /* APIC mode */
1277                                         Return (PSa)                  /* PIC Mode */
1278                                 } /* end _PRT */
1279                         } /* end PBRa */
1280
1281                         Device(PE20) {
1282                                 Name(_ADR, 0x00150000)
1283                                 Name(_PRW, Package() {0x18, 4})
1284                                 Method(_PRT,0) {
1285                                         If(PMOD){ Return(APE0) }   /* APIC mode */
1286                                         Return (PE0)                  /* PIC Mode */
1287                                 } /* end _PRT */
1288                         } /* end PE20 */
1289                         Device(PE21) {
1290                                 Name(_ADR, 0x00150001)
1291                                 Name(_PRW, Package() {0x18, 4})
1292                                 Method(_PRT,0) {
1293                                         If(PMOD){ Return(APE1) }   /* APIC mode */
1294                                         Return (PE1)                  /* PIC Mode */
1295                                 } /* end _PRT */
1296                         } /* end PE21 */
1297                         Device(PE22) {
1298                                 Name(_ADR, 0x00150002)
1299                                 Name(_PRW, Package() {0x18, 4})
1300                                 Method(_PRT,0) {
1301                                         If(PMOD){ Return(APE2) }   /* APIC mode */
1302                                         Return (APE2)                  /* PIC Mode */
1303                                 } /* end _PRT */
1304                         } /* end PE22 */
1305                         Device(PE23) {
1306                                 Name(_ADR, 0x00150003)
1307                                 Name(_PRW, Package() {0x18, 4})
1308                                 Method(_PRT,0) {
1309                                         If(PMOD){ Return(APE3) }   /* APIC mode */
1310                                         Return (PE3)                  /* PIC Mode */
1311                                 } /* end _PRT */
1312                         } /* end PE23 */
1313
1314                         /* PCI slot 1, 2, 3 */
1315                         Device(PIBR) {
1316                                 Name(_ADR, 0x00140004)
1317                                 Name(_PRW, Package() {0x18, 4})
1318
1319                                 Method(_PRT, 0) {
1320                                         Return (PCIB)
1321                                 }
1322                         }
1323
1324                         /* Describe the Southbridge devices */
1325                         Device(STCR) {
1326                                 Name(_ADR, 0x00110000)
1327                                 #include "acpi/sata.asl"
1328                         } /* end STCR */
1329
1330                         Device(UOH1) {
1331                                 Name(_ADR, 0x00120000)
1332                                 Name(_PRW, Package() {0x0B, 3})
1333                         } /* end UOH1 */
1334
1335                         Device(UOH2) {
1336                                 Name(_ADR, 0x00120002)
1337                                 Name(_PRW, Package() {0x0B, 3})
1338                         } /* end UOH2 */
1339
1340                         Device(UOH3) {
1341                                 Name(_ADR, 0x00130000)
1342                                 Name(_PRW, Package() {0x0B, 3})
1343                         } /* end UOH3 */
1344
1345                         Device(UOH4) {
1346                                 Name(_ADR, 0x00130002)
1347                                 Name(_PRW, Package() {0x0B, 3})
1348                         } /* end UOH4 */
1349
1350                         Device(UOH5) {
1351                                 Name(_ADR, 0x00160000)
1352                                 Name(_PRW, Package() {0x0B, 3})
1353                         } /* end UOH5 */
1354
1355                         Device(UOH6) {
1356                                 Name(_ADR, 0x00160002)
1357                                 Name(_PRW, Package() {0x0B, 3})
1358                         } /* end UOH5 */
1359
1360                         Device(UEH1) {
1361                                 Name(_ADR, 0x00140005)
1362                                 Name(_PRW, Package() {0x0B, 3})
1363                         } /* end UEH1 */
1364
1365                         Device(SBUS) {
1366                                 Name(_ADR, 0x00140000)
1367                         } /* end SBUS */
1368
1369                         /* Primary (and only) IDE channel */
1370                         Device(IDEC) {
1371                                 Name(_ADR, 0x00140001)
1372                                 #include "acpi/ide.asl"
1373                         } /* end IDEC */
1374
1375                         Device(AZHD) {
1376                                 Name(_ADR, 0x00140002)
1377                                 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1378                                         Field(AZPD, AnyAcc, NoLock, Preserve) {
1379                                         offset (0x42),
1380                                         NSDI, 1,
1381                                         NSDO, 1,
1382                                         NSEN, 1,
1383                                         offset (0x44),
1384                                         IPCR, 4,
1385                                         offset (0x54),
1386                                         PWST, 2,
1387                                         , 6,
1388                                         PMEB, 1,
1389                                         , 6,
1390                                         PMST, 1,
1391                                         offset (0x62),
1392                                         MMCR, 1,
1393                                         offset (0x64),
1394                                         MMLA, 32,
1395                                         offset (0x68),
1396                                         MMHA, 32,
1397                                         offset (0x6C),
1398                                         MMDT, 16,
1399                                 }
1400
1401                                 Method(_INI) {
1402                                         If(LEqual(OSTP,3)){   /* If we are running Linux */
1403                                                 Store(zero, NSEN)
1404                                                 Store(one, NSDO)
1405                                                 Store(one, NSDI)
1406                                         }
1407                                 }
1408                         } /* end AZHD */
1409
1410                         Device(LIBR) {
1411                                 Name(_ADR, 0x00140003)
1412                                 /* Method(_INI) {
1413                                 *       DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1414                                 } */ /* End Method(_SB.SBRDG._INI) */
1415
1416                                 /* Real Time Clock Device */
1417                                 Device(RTC0) {
1418                                         Name(_HID, EISAID("PNP0B01"))   /* AT Real Time Clock */
1419                                         Name(_CRS, ResourceTemplate() {
1420                                                 IRQNoFlags(){8}
1421                                                 IO(Decode16,0x0070, 0x0070, 0, 2)
1422                                                 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1423                                         })
1424                                 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1425
1426                                 Device(TMR) {   /* Timer */
1427                                         Name(_HID,EISAID("PNP0100"))    /* System Timer */
1428                                         Name(_CRS, ResourceTemplate() {
1429                                                 IRQNoFlags(){0}
1430                                                 IO(Decode16, 0x0040, 0x0040, 0, 4)
1431                                                 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1432                                         })
1433                                 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1434
1435                                 Device(SPKR) {  /* Speaker */
1436                                         Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
1437                                         Name(_CRS, ResourceTemplate() {
1438                                                 IO(Decode16, 0x0061, 0x0061, 0, 1)
1439                                         })
1440                                 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1441
1442                                 Device(PIC) {
1443                                         Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
1444                                         Name(_CRS, ResourceTemplate() {
1445                                                 IRQNoFlags(){2}
1446                                                 IO(Decode16,0x0020, 0x0020, 0, 2)
1447                                                 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1448                                                 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1449                                                 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1450                                         })
1451                                 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1452
1453                                 Device(MAD) { /* 8257 DMA */
1454                                         Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
1455                                         Name(_CRS, ResourceTemplate() {
1456                                                 DMA(Compatibility,BusMaster,Transfer8){4}
1457                                                 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1458                                                 IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
1459                                                 IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
1460                                                 IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
1461                                                 IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
1462                                                 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1463                                         }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1464                                 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1465
1466                                 Device(COPR) {
1467                                         Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
1468                                         Name(_CRS, ResourceTemplate() {
1469                                                 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1470                                                 IRQNoFlags(){13}
1471                                         })
1472                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1473 #if 0
1474                                 Device(HPTM) {
1475                                         Name(_HID,EISAID("PNP0103"))
1476                                         Name(CRS,ResourceTemplate()     {
1477                                                 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)     /* 1kb reserved space */
1478                                         })
1479                                         Method(_STA, 0) {
1480                                                 Return(0x0F) /* sata is visible */
1481                                         }
1482                                         Method(_CRS, 0) {
1483                                                 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1484                                                 Store(HPBA, HPBA)
1485                                                 Return(CRS)
1486                                         }
1487                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1488 #endif
1489                         } /* end LIBR */
1490
1491                         Device(HPBR) {
1492                                 Name(_ADR, 0x00140004)
1493                         } /* end HostPciBr */
1494
1495                         Device(ACAD) {
1496                                 Name(_ADR, 0x00140005)
1497                         } /* end Ac97audio */
1498
1499                         Device(ACMD) {
1500                                 Name(_ADR, 0x00140006)
1501                         } /* end Ac97modem */
1502
1503                         Name(CRES, ResourceTemplate() {
1504                                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1505
1506                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1507                                         0x0000,                 /* address granularity */
1508                                         0x0000,                 /* range minimum */
1509                                         0x0CF7,                 /* range maximum */
1510                                         0x0000,                 /* translation */
1511                                         0x0CF8                  /* length */
1512                                 )
1513
1514                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1515                                         0x0000,                 /* address granularity */
1516                                         0x0D00,                 /* range minimum */
1517                                         0xFFFF,                 /* range maximum */
1518                                         0x0000,                 /* translation */
1519                                         0xF300                  /* length */
1520                                 )
1521 #if 0
1522                                 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1523                                 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)   /* VGA memory space */
1524                                 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)   /* Assume C0000-E0000 empty */
1525                                 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
1526
1527                                 /* DRAM Memory from 1MB to TopMem */
1528                                 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)   /* 1MB to TopMem */
1529
1530                                 /* BIOS space just below 4GB */
1531                                 DWORDMemory(
1532                                         ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1533                                         0x00,                   /* Granularity */
1534                                         0x00000000,             /* Min */
1535                                         0x00000000,             /* Max */
1536                                         0x00000000,             /* Translation */
1537                                         0x00000000,             /* Max-Min, RLEN */
1538                                         ,,
1539                                         PCBM
1540                                 )
1541
1542                                 /* DRAM memory from 4GB to TopMem2 */
1543                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1544                                         0xFFFFFFFF,             /* Granularity */
1545                                         0x00000000,             /*  Min */
1546                                         0x00000000,             /* Max */
1547                                         0x00000000,             /* Translation */
1548                                         0x00000000,             /* Max-Min, RLEN */
1549                                         ,,
1550                                         DMHI
1551                                 )
1552
1553                                 /* BIOS space just below 16EB */
1554                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1555                                         0xFFFFFFFF,             /* Granularity */
1556                                         0x00000000,             /* Min */
1557                                         0x00000000,             /*  Max */
1558                                         0x00000000,             /* Translation */
1559                                         0x00000000,             /* Max-Min, RLEN */
1560                                         ,,
1561                                         PEBM
1562                                 )
1563 #endif
1564                                 /* memory space for PCI BARs below 4GB */
1565                                 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1566                         }) /* End Name(_SB.PCI0.CRES) */
1567
1568                         Method(_CRS, 0) {
1569                                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1570 #if 0
1571                                 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1572                                 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1573                                 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1574                                 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1575                                 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1576                                 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1577
1578                                 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1579                                 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1580                                 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1581                                 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1582
1583                                 If(LGreater(LOMH, 0xC0000)){
1584                                         Store(0xC0000, EM1B)    /* Hole above C0000 and below E0000 */
1585                                         Subtract(LOMH, 0xC0000, EM1L)   /* subtract start, assumes allocation from C0000 going up */
1586                                 }
1587
1588                                 /* Set size of memory from 1MB to TopMem */
1589                                 Subtract(TOM1, 0x100000, DMLL)
1590
1591                                 /*
1592                                 * If(LNotEqual(TOM2, 0x00000000)){
1593                                 *       Store(0x100000000,DMHB)                 DRAM from 4GB to TopMem2
1594                                 *       Subtract(TOM2, 0x100000000, DMHL)
1595                                 * }
1596                                 */
1597
1598                                 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1599                                 If(LEqual(TOM2, 0x00000000)){
1600                                         Store(PBAD,PBMB)                        /* Reserve the "BIOS" space */
1601                                         Store(PBLN,PBML)
1602                                 }
1603                                 Else {  /* Otherwise, put the BIOS just below 16EB */
1604                                         ShiftLeft(PBAD,16,EBMB)         /* Reserve the "BIOS" space */
1605                                         Store(PBLN,EBML)
1606                                 }
1607 #endif
1608                                 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1609                                 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1610                                 /*
1611                                  * Declare memory between TOM1 and 4GB as available
1612                                  * for PCI MMIO.
1613                                  * Use ShiftLeft to avoid 64bit constant (for XP).
1614                                  * This will work even if the OS does 32bit arithmetic, as
1615                                  * 32bit (0x00000000 - TOM1) will wrap and give the same
1616                                  * result as 64bit (0x100000000 - TOM1).
1617                                  */
1618                                 Store(TOM1, MM1B)
1619                                 ShiftLeft(0x10000000, 4, Local0)
1620                                 Subtract(Local0, TOM1, Local0)
1621                                 Store(Local0, MM1L)
1622
1623                                 Return(CRES) /* note to change the Name buffer */
1624                         }  /* end of Method(_SB.PCI0._CRS) */
1625
1626                         /*
1627                         *
1628                         *               FIRST METHOD CALLED UPON BOOT
1629                         *
1630                         *  1. If debugging, print current OS and ACPI interpreter.
1631                         *  2. Get PCI Interrupt routing from ACPI VSM, this
1632                         *     value is based on user choice in BIOS setup.
1633                         */
1634                         Method(_INI, 0) {
1635                                 /* DBGO("\\_SB\\_INI\n") */
1636                                 /* DBGO("   DSDT.ASL code from ") */
1637                                 /* DBGO(__DATE__) */
1638                                 /* DBGO(" ") */
1639                                 /* DBGO(__TIME__) */
1640                                 /* DBGO("\n   Sleep states supported: ") */
1641                                 /* DBGO("\n") */
1642                                 /* DBGO("   \\_OS=") */
1643                                 /* DBGO(\_OS) */
1644                                 /* DBGO("\n   \\_REV=") */
1645                                 /* DBGO(\_REV) */
1646                                 /* DBGO("\n") */
1647
1648                                 /* Determine the OS we're running on */
1649                                 CkOT()
1650
1651                                 /* On older chips, clear PciExpWakeDisEn */
1652                                 /*if (LLessEqual(\SBRI, 0x13)) {
1653                                 *       Store(0,\PWDE)
1654                                 * }
1655                                 */
1656                         } /* End Method(_SB._INI) */
1657                 } /* End Device(PCI0)  */
1658
1659                 Device(PWRB) {  /* Start Power button device */
1660                         Name(_HID, EISAID("PNP0C0C"))
1661                         Name(_UID, 0xAA)
1662                         Name(_PRW, Package () {3, 0x04})        /* wake from S1-S4 */
1663                         Name(_STA, 0x0B) /* sata is invisible */
1664                 }
1665         } /* End \_SB scope */
1666
1667         Scope(\_SI) {
1668                 Method(_SST, 1) {
1669                         /* DBGO("\\_SI\\_SST\n") */
1670                         /* DBGO("   New Indicator state: ") */
1671                         /* DBGO(Arg0) */
1672                         /* DBGO("\n") */
1673                 }
1674         } /* End Scope SI */
1675 #if 0
1676         /* SMBUS Support */
1677         Mutex (SBX0, 0x00)
1678         OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1679                 Field (SMB0, ByteAcc, NoLock, Preserve) {
1680                         HSTS,   8, /* SMBUS status */
1681                         SSTS,   8,  /* SMBUS slave status */
1682                         HCNT,   8,  /* SMBUS control */
1683                         HCMD,   8,  /* SMBUS host cmd */
1684                         HADD,   8,  /* SMBUS address */
1685                         DAT0,   8,  /* SMBUS data0 */
1686                         DAT1,   8,  /* SMBUS data1 */
1687                         BLKD,   8,  /* SMBUS block data */
1688                         SCNT,   8,  /* SMBUS slave control */
1689                         SCMD,   8,  /* SMBUS shaow cmd */
1690                         SEVT,   8,  /* SMBUS slave event */
1691                         SDAT,   8  /* SMBUS slave data */
1692         }
1693
1694         Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1695                 Store (0x1E, HSTS)
1696                 Store (0xFA, Local0)
1697                 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1698                         Stall (0x64)
1699                         Decrement (Local0)
1700                 }
1701
1702                 Return (Local0)
1703         }
1704
1705         Method (SWTC, 1, NotSerialized) {
1706                 Store (Arg0, Local0)
1707                 Store (0x07, Local2)
1708                 Store (One, Local1)
1709                 While (LEqual (Local1, One)) {
1710                         Store (And (HSTS, 0x1E), Local3)
1711                         If (LNotEqual (Local3, Zero)) { /* read sucess */
1712                                 If (LEqual (Local3, 0x02)) {
1713                                         Store (Zero, Local2)
1714                                 }
1715
1716                                 Store (Zero, Local1)
1717                         }
1718                         Else {
1719                                 If (LLess (Local0, 0x0A)) { /* read failure */
1720                                         Store (0x10, Local2)
1721                                         Store (Zero, Local1)
1722                                 }
1723                                 Else {
1724                                         Sleep (0x0A) /* 10 ms, try again */
1725                                         Subtract (Local0, 0x0A, Local0)
1726                                 }
1727                         }
1728                 }
1729
1730                 Return (Local2)
1731         }
1732
1733         Method (SMBR, 3, NotSerialized) {
1734                 Store (0x07, Local0)
1735                 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1736                         Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1737                         If (LEqual (Local0, Zero)) {
1738                                 Release (SBX0)
1739                                 Return (0x0)
1740                         }
1741
1742                         Store (0x1F, HSTS)
1743                         Store (Or (ShiftLeft (Arg1, One), One), HADD)
1744                         Store (Arg2, HCMD)
1745                         If (LEqual (Arg0, 0x07)) {
1746                                 Store (0x48, HCNT) /* read byte */
1747                         }
1748
1749                         Store (SWTC (0x03E8), Local1) /* 1000 ms */
1750                         If (LEqual (Local1, Zero)) {
1751                                 If (LEqual (Arg0, 0x07)) {
1752                                         Store (DAT0, Local0)
1753                                 }
1754                         }
1755                         Else {
1756                                 Store (Local1, Local0)
1757                         }
1758
1759                         Release (SBX0)
1760                 }
1761
1762                 /* DBGO("the value of SMBusData0 register ") */
1763                 /* DBGO(Arg2) */
1764                 /* DBGO(" is ") */
1765                 /* DBGO(Local0) */
1766                 /* DBGO("\n") */
1767
1768                 Return (Local0)
1769         }
1770
1771         /* THERMAL */
1772         Scope(\_TZ) {
1773                 Name (KELV, 2732)
1774                 Name (THOT, 800)
1775                 Name (TCRT, 850)
1776
1777                 ThermalZone(TZ00) {
1778                         Method(_AC0,0) {        /* Active Cooling 0 (0=highest fan speed) */
1779                                 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1780                                 Return(Add(0, 2730))
1781                         }
1782                         Method(_AL0,0) {        /* Returns package of cooling device to turn on */
1783                                 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1784                                 Return(Package() {\_TZ.TZ00.FAN0})
1785                         }
1786                         Device (FAN0) {
1787                                 Name(_HID, EISAID("PNP0C0B"))
1788                                 Name(_PR0, Package() {PFN0})
1789                         }
1790
1791                         PowerResource(PFN0,0,0) {
1792                                 Method(_STA) {
1793                                         Store(0xF,Local0)
1794                                         Return(Local0)
1795                                 }
1796                                 Method(_ON) {
1797                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1798                                 }
1799                                 Method(_OFF) {
1800                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1801                                 }
1802                         }
1803
1804                         Method(_HOT,0) {        /* return hot temp in tenths degree Kelvin */
1805                                 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1806                                 Return (Add (THOT, KELV))
1807                         }
1808                         Method(_CRT,0) {        /* return critical temp in tenths degree Kelvin */
1809                                 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1810                                 Return (Add (TCRT, KELV))
1811                         }
1812                         Method(_TMP,0) {        /* return current temp of this zone */
1813                                 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1814                                 If (LGreater (Local0, 0x10)) {
1815                                         Store (Local0, Local1)
1816                                 }
1817                                 Else {
1818                                         Add (Local0, THOT, Local0)
1819                                         Return (Add (400, KELV))
1820                                 }
1821
1822                                 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1823                                 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1824                                 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1825                                 If (LGreater (Local0, 0x10)) {
1826                                         If (LGreater (Local0, Local1)) {
1827                                                 Store (Local0, Local1)
1828                                         }
1829
1830                                         Multiply (Local1, 10, Local1)
1831                                         Return (Add (Local1, KELV))
1832                                 }
1833                                 Else {
1834                                         Add (Local0, THOT, Local0)
1835                                         Return (Add (400 , KELV))
1836                                 }
1837                         } /* end of _TMP */
1838                 } /* end of TZ00 */
1839         }
1840 #endif
1841 }
1842 /* End of ASL file */