blah: seabios quirks (not here) WIP
authorBernhard Urban <lewurm@gmail.com>
Fri, 6 Apr 2012 12:27:49 +0000 (14:27 +0200)
committerBernhard Urban <lewurm@gmail.com>
Fri, 6 Apr 2012 12:27:49 +0000 (14:27 +0200)
- set some static value for tsc configure
-> something wrong at coreboot init?
- keyboard not found, so I uncommented stuff in boot.c
  I don't have a vga anyway...

src/mainboard/asus/m5a99x-evo/dsdt.asl
src/mainboard/asus/m5a99x-evo/mainboard.c

index 88354cf93146b5dc2e2b35fc1b7351984a1b61f7..00169ab3481cea7dfdda8502c7635bf9b56cf394 100644 (file)
@@ -98,6 +98,24 @@ DefinitionBlock (
                        ) {
                        #include "acpi/cpstate.asl"
                }
+
+               Processor(
+                       CPU4,           /* name space name */
+                       4,              /* Unique number for this processor */
+                       0x0000,         /* PBLK system I/O address !hardcoded! */
+                       0x00            /* PBLKLEN for boot processor */
+                       ) {
+                       #include "acpi/cpstate.asl"
+               }
+
+               Processor(
+                       CPU5,           /* name space name */
+                       5,              /* Unique number for this processor */
+                       0x0000,         /* PBLK system I/O address !hardcoded! */
+                       0x00            /* PBLKLEN for boot processor */
+                       ) {
+                       #include "acpi/cpstate.asl"
+               }
        } /* End _PR scope */
 
        /* PIC IRQ mapping registers, C00h-C01h. */
index 3a4465423fd2e3faa809547e0fbdc71f5e6b62d4..12e3c85dad28bb11f97dac1db45aee14d835b3d3 100644 (file)
@@ -55,6 +55,20 @@ static void m5a99x_evo_enable(device_t dev)
 
        printk(BIOS_INFO, "Mainboard ASUS M5A99X-EVO Enable. dev=0x%p\n", dev);
 
+       msr_t msr, msr2;
+
+       /* TOP_MEM: the top of DRAM below 4G */
+       msr = rdmsr(TOP_MEM);
+       printk
+           (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+            __func__, msr.lo, msr.hi);
+
+       /* TOP_MEM2: the top of DRAM above 4G */
+       msr2 = rdmsr(TOP_MEM2);
+       printk
+           (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+            __func__, msr2.lo, msr2.hi);
+
        set_pcie_dereset();
 }