) {
#include "acpi/cpstate.asl"
}
+
+ Processor(
+ CPU4, /* name space name */
+ 4, /* Unique number for this processor */
+ 0x0000, /* PBLK system I/O address !hardcoded! */
+ 0x00 /* PBLKLEN for boot processor */
+ ) {
+ #include "acpi/cpstate.asl"
+ }
+
+ Processor(
+ CPU5, /* name space name */
+ 5, /* Unique number for this processor */
+ 0x0000, /* PBLK system I/O address !hardcoded! */
+ 0x00 /* PBLKLEN for boot processor */
+ ) {
+ #include "acpi/cpstate.asl"
+ }
} /* End _PR scope */
/* PIC IRQ mapping registers, C00h-C01h. */
printk(BIOS_INFO, "Mainboard ASUS M5A99X-EVO Enable. dev=0x%p\n", dev);
+ msr_t msr, msr2;
+
+ /* TOP_MEM: the top of DRAM below 4G */
+ msr = rdmsr(TOP_MEM);
+ printk
+ (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr.lo, msr.hi);
+
+ /* TOP_MEM2: the top of DRAM above 4G */
+ msr2 = rdmsr(TOP_MEM2);
+ printk
+ (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+ __func__, msr2.lo, msr2.hi);
+
set_pcie_dereset();
}