src/mainboard/asus/m2v-mx_se/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2006 MSI
   7  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
   8  * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 unsigned int get_sbdn(unsigned bus);
  26
  27 #if CONFIG_K8_REV_F_SUPPORT == 1
  28 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  29 #endif
  30
  31 #include <stdint.h>
  32 #include <string.h>
  33 #include <device/pci_def.h>
  34 #include <arch/io.h>
  35 #include <device/pnp_def.h>
  36 #include <arch/romcc_io.h>
  37 #include <cpu/amd/mtrr.h>
  38 #include <cpu/x86/lapic.h>
  39 #include <pc80/mc146818rtc.h>
  40 #include <console/console.h>
  41 #include <cpu/amd/model_fxx_rev.h>
  42 #include "northbridge/amd/amdk8/raminit.h"
  43 #include "cpu/amd/model_fxx/apic_timer.c"
  44 #include "lib/delay.c"
  45 #include "northbridge/amd/amdk8/reset_test.c"
  46 #include "northbridge/amd/amdk8/debug.c"
  47 #include "superio/ite/it8712f/early_serial.c"
  48 #include "southbridge/via/vt8237r/early_smbus.c"
  49 #include "cpu/x86/mtrr/earlymtrr.c"
  50 #include "cpu/x86/bist.h"
  51 #include "northbridge/amd/amdk8/setup_resource_map.c"
  52 #include <spd.h>
  53
  54 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
  55 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  58 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #include "southbridge/via/k8t890/early_car.c"
  66 #include "northbridge/amd/amdk8/amdk8.h"
  67 #include "northbridge/amd/amdk8/incoherent_ht.c"
  68 #include "northbridge/amd/amdk8/coherent_ht.c"
  69 #include "northbridge/amd/amdk8/raminit_f.c"
  70 #include "lib/generic_sdram.c"
  71 #include "cpu/amd/dualcore/dualcore.c"
  72 #include "cpu/amd/car/post_cache_as_ram.c"
  73 #include "cpu/amd/model_fxx/init_cpus.c"
  74
  75 #define SB_VFSMAF 0
  76
  77 static void ldtstop_sb(void)
  78 {
  79         print_debug("toggle LDTSTP#\n");
  80
  81         /* fix errata #181, disable DRAM controller it will get enabled later */
  82         u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94);
  83         tmp |= (( 1 << 14) | (1 << 3));
  84         pci_write_config8(PCI_DEV(0, 0x18, 2), 0x94, tmp);
  85
  86         u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
  87         reg = reg ^ (1 << 0);
  88         outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
  89         reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
  90         print_debug("done\n");
  91 }
  92
  93 #include "cpu/amd/model_fxx/fidvid.c"
  94 #include "northbridge/amd/amdk8/resourcemap.c"
  95
  96 void soft_reset(void)
  97 {
  98         uint8_t tmp;
  99
 100         set_bios_reset();
 101         print_debug("soft reset \n");
 102
 103         /* PCI reset */
 104         tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
 105         tmp |= 0x01;
 106         /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
 107         pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 108
 109         while (1) {
 110                 /* daisy daisy ... */
 111                 hlt();
 112         }
 113 }
 114
 115 unsigned int get_sbdn(unsigned bus)
 116 {
 117         device_t dev;
 118
 119         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 120                                         PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
 121         return (dev >> 15) & 0x1f;
 122 }
 123
 124 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 125 {
 126         static const uint16_t spd_addr[] = {
 127                 // Node 0
 128                 DIMM0, DIMM2, 0, 0,
 129                 DIMM1, DIMM3, 0, 0,
 130                 // Node 1
 131                 DIMM4, DIMM6, 0, 0,
 132                 DIMM5, DIMM7, 0, 0,
 133         };
 134         unsigned bsp_apicid = 0;
 135         int needs_reset = 0;
 136         struct sys_info *sysinfo =
 137             (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 138
 139         it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 140         it8712f_kill_watchdog();
 141         it8712f_enable_3vsbsw();
 142         console_init();
 143         enable_rom_decode();
 144
 145         printk(BIOS_INFO, "now booting... \n");
 146
 147         if (bist == 0)
 148                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 149
 150         /* Halt if there was a built in self test failure. */
 151         report_bist_failure(bist);
 152         setup_default_resource_map();
 153         setup_coherent_ht_domain();
 154         wait_all_core0_started();
 155
 156         printk(BIOS_INFO, "now booting... All core 0 started\n");
 157
 158 #if CONFIG_LOGICAL_CPUS==1
 159         /* It is said that we should start core1 after all core0 launched. */
 160         start_other_cores();
 161         wait_all_other_cores_started(bsp_apicid);
 162 #endif
 163         init_timer();
 164         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 165
 166         needs_reset = optimize_link_coherent_ht();
 167         print_debug_hex8(needs_reset);
 168         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 169         print_debug_hex8(needs_reset);
 170         needs_reset |= k8t890_early_setup_ht();
 171         print_debug_hex8(needs_reset);
 172
 173         vt8237_early_network_init(NULL);
 174         vt8237_early_spi_init();
 175
 176         if (needs_reset) {
 177                 printk(BIOS_DEBUG, "ht reset -\n");
 178                 soft_reset();
 179                 printk(BIOS_DEBUG, "FAILED!\n");
 180         }
 181
 182         /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
 183         /* allow LDT STOP asserts */
 184         vt8237_sb_enable_fid_vid();
 185
 186         enable_fid_change();
 187         print_debug("after enable_fid_change\n");
 188
 189         init_fidvid_bsp(bsp_apicid);
 190
 191         /* Stop the APs so we can start them later in init. */
 192         allow_all_aps_stop(bsp_apicid);
 193
 194         /* It's the time to set ctrl now. */
 195         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 196         enable_smbus();
 197         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 198         post_cache_as_ram();
 199 }