2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 ## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, write to the Free Software
20 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
24 default CONFIG_XIP_ROM_SIZE = 128 * 1024
25 include /config/nofailovercalculation.lb
30 if CONFIG_HAVE_ACPI_TABLES
33 depends "$(CONFIG_MAINBOARD)/dsdt.asl"
34 action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
35 action "mv dsdt.hex dsdt.c"
41 makerule ./cache_as_ram_auto.o
42 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
43 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
46 makerule ./cache_as_ram_auto.inc
47 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
48 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
49 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
50 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
54 if CONFIG_USE_FALLBACK_IMAGE
55 mainboardinit cpu/x86/16bit/entry16.inc
56 ldscript /cpu/x86/16bit/entry16.lds
57 mainboardinit southbridge/via/k8t890/romstrap.inc
58 ldscript /southbridge/via/k8t890/romstrap.lds
61 mainboardinit cpu/x86/32bit/entry32.inc
64 ldscript /cpu/x86/32bit/entry32.lds
67 ldscript /cpu/amd/car/cache_as_ram.lds
70 if CONFIG_USE_FALLBACK_IMAGE
71 mainboardinit cpu/x86/16bit/reset16.inc
72 ldscript /cpu/x86/16bit/reset16.lds
74 mainboardinit cpu/x86/32bit/reset32.inc
75 ldscript /cpu/x86/32bit/reset32.lds
78 mainboardinit cpu/amd/car/cache_as_ram.inc
80 if CONFIG_USE_FALLBACK_IMAGE
81 ldscript /arch/i386/lib/failover.lds
85 initobject cache_as_ram_auto.o
87 mainboardinit ./cache_as_ram_auto.inc
92 chip northbridge/amd/amdk8/root_complex # Root complex
93 device apic_cluster 0 on # APIC cluster
94 chip cpu/amd/socket_AM2 # CPU
95 device apic 0 on end # APIC
98 device pci_domain 0 on # PCI domain
99 chip northbridge/amd/amdk8 # mc0
100 device pci 18.0 on # Northbridge
101 # Devices on link 0, link 0 == LDT 0
102 chip southbridge/via/vt8237r # Southbridge
103 register "ide0_enable" = "1" # Enable IDE channel 0
104 register "ide1_enable" = "1" # Enable IDE channel 1
105 register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
106 register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
107 register "fn_ctrl_lo" = "0xc0" # Enable SB functions
108 register "fn_ctrl_hi" = "0x1d" # Enable SB functions
109 device pci 0.0 on end # HT
110 device pci f.1 on end # IDE
111 device pci 11.0 on # LPC
112 chip drivers/generic/generic # DIMM 0-0-0
115 chip drivers/generic/generic # DIMM 0-0-1
118 chip drivers/generic/generic # DIMM 0-1-0
121 chip drivers/generic/generic # DIMM 0-1-1
124 chip superio/ite/it8712f # Super I/O
125 device pnp 2e.0 on # Floppy
130 device pnp 2e.1 on # Com1
134 device pnp 2e.2 off # Com2
138 device pnp 2e.3 on # Parallel port
142 device pnp 2e.4 on # Environment controller
147 device pnp 2e.5 off end # PS/2 keyboard
148 device pnp 2e.6 off end # PS/2 mouse
149 device pnp 2e.7 off end # GPIO config
150 device pnp 2e.8 off end # Midi port
151 device pnp 2e.9 off end # Game port
152 device pnp 2e.a off end # IR
155 device pci 12.0 on end # VIA LAN
156 device pci 13.0 on end # br
157 device pci 13.1 on end # br2 need to have it here to discover it
159 chip southbridge/via/k8t890 # "Southbridge" K8M890
162 device pci 18.1 on end
163 device pci 18.2 on end
164 device pci 18.3 on end