2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 /* Used by it8712f_enable_serial(). */
28 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
30 /* Used by raminit. */
31 #define QRANK_DIMM_SUPPORT 1
33 /* Turn this on for SMBus debugging output. */
36 #if CONFIG_LOGICAL_CPUS == 1
37 #define SET_NB_CFG_54 1
42 #include <device/pci_def.h>
44 #include <device/pnp_def.h>
45 #include <arch/romcc_io.h>
46 #include <cpu/x86/lapic.h>
47 #include "option_table.h"
48 #include "pc80/mc146818rtc_early.c"
49 #include "cpu/x86/lapic/boot_cpu.c"
50 #include "northbridge/amd/amdk8/reset_test.c"
51 #include "superio/ite/it8712f/it8712f_early_serial.c"
53 #if CONFIG_USE_FAILOVER_IMAGE == 0
55 /* Used by ck894_early_setup(). */
58 #include <cpu/amd/model_fxx_rev.h>
59 #include "pc80/serial.c"
60 #include "arch/i386/lib/console.c"
61 #include "ram/ramtest.c"
62 #include "northbridge/amd/amdk8/incoherent_ht.c"
63 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
64 #include "northbridge/amd/amdk8/raminit.h"
65 #include "cpu/amd/model_fxx/apic_timer.c"
66 #include "lib/delay.c"
67 #include "northbridge/amd/amdk8/debug.c"
68 #include "cpu/amd/mtrr/amd_earlymtrr.c"
69 #include "cpu/x86/bist.h"
70 #include "northbridge/amd/amdk8/setup_resource_map.c"
71 #include "northbridge/amd/amdk8/coherent_ht.c"
72 #include "cpu/amd/dualcore/dualcore.c"
74 static void memreset_setup(void)
79 static void memreset(int controllers, const struct mem_controller *ctrl)
84 static inline void activate_spd_rom(const struct mem_controller *ctrl)
89 static inline int spd_read_byte(unsigned device, unsigned address)
91 return smbus_read_byte(device, address);
94 #include "northbridge/amd/amdk8/raminit.c"
95 #include "sdram/generic_sdram.c"
96 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
97 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
98 #include "cpu/amd/car/copy_and_run.c"
99 #include "cpu/amd/car/post_cache_as_ram.c"
100 #include "cpu/amd/model_fxx/init_cpus.c"
102 #endif /* CONFIG_USE_FAILOVER_IMAGE */
104 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \
105 || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
107 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
108 #include "northbridge/amd/amdk8/early_ht.c"
110 static void sio_setup(void)
116 /* Subject decoding */
117 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
119 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
121 /* LPC Positive Decode 0 */
122 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
123 dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */
124 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
127 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
129 unsigned last_boot_normal_x = last_boot_normal();
131 /* Is this a CPU only reset? Or is this a secondary CPU? */
132 if ((cpu_init_detectedx) || (!boot_cpu())) {
133 if (last_boot_normal_x) {
140 /* Nothing special needs to be done to find bus 0 */
141 /* Allow the HT devices to be found */
142 enumerate_ht_chain();
146 /* Setup the ck804 */
149 /* Is this a deliberate reset by the BIOS? */
150 if (bios_reset_detected() && last_boot_normal_x) {
154 /* This is the primary CPU. How should I boot? */
155 else if (do_normal_boot()) {
162 __asm__ volatile ("jmp __normal_image"
164 :"a" (bist), "b"(cpu_init_detectedx) /* inputs */
169 #if CONFIG_HAVE_FAILOVER_BOOT == 1
170 __asm__ volatile ("jmp __fallback_image"
172 :"a" (bist), "b"(cpu_init_detectedx) /* inputs */
178 #endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */
180 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
182 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
184 #if CONFIG_HAVE_FAILOVER_BOOT == 1
185 #if CONFIG_USE_FAILOVER_IMAGE == 1
186 failover_process(bist, cpu_init_detectedx);
188 real_main(bist, cpu_init_detectedx);
191 #if CONFIG_USE_FALLBACK_IMAGE == 1
192 failover_process(bist, cpu_init_detectedx);
194 real_main(bist, cpu_init_detectedx);
198 #if CONFIG_USE_FAILOVER_IMAGE == 0
199 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
201 static const uint16_t spd_addr[] = {
202 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
203 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
204 #if CONFIG_MAX_PHYSICAL_CPUS > 1
205 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
206 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
211 unsigned nodes, bsp_apicid = 0;
212 struct mem_controller ctrl[8];
215 bsp_apicid = init_cpus(cpu_init_detectedx);
217 it8712f_24mhz_clkin();
218 it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
222 /* Halt if there was a built in self test failure */
223 report_bist_failure(bist);
226 dump_pci_device(PCI_DEV(0, 0x18, 0));
229 needs_reset = setup_coherent_ht_domain();
231 wait_all_core0_started();
232 #if CONFIG_LOGICAL_CPUS==1
233 /* It is said that we should start core1 after all core0 launched. */
235 wait_all_other_cores_started(bsp_apicid);
238 needs_reset |= ht_setup_chains_x();
239 needs_reset |= ck804_early_setup_x();
242 print_info("ht reset -\r\n");
246 allow_all_aps_stop(bsp_apicid);
249 /* It's the time to set ctrl now. */
250 fill_mem_ctrl(nodes, ctrl, spd_addr);
255 dump_spd_registers(&ctrl[0]);
256 dump_smbus_registers();
260 sdram_initialize(nodes, ctrl);
269 #endif /* CONFIG_USE_FAILOVER_IMAGE */