1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
17 if CONFIG_HAVE_PIRQ_TABLE
24 # makerule ./failover.E
25 # depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
26 # action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
29 # makerule ./failover.inc
30 # depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
31 # action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
35 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
36 action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
39 depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
40 action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
44 ## Build our 16 bit and 32 bit coreboot entry code
46 mainboardinit cpu/x86/16bit/entry16.inc
47 mainboardinit cpu/x86/32bit/entry32.inc
48 ldscript /cpu/x86/16bit/entry16.lds
49 ldscript /cpu/x86/32bit/entry32.lds
52 ## Build our reset vector (This is where coreboot is entered)
54 if CONFIG_USE_FALLBACK_IMAGE
55 mainboardinit cpu/x86/16bit/reset16.inc
56 ldscript /cpu/x86/16bit/reset16.lds
58 mainboardinit cpu/x86/32bit/reset32.inc
59 ldscript /cpu/x86/32bit/reset32.lds
62 ### Should this be in the northbridge code?
63 mainboardinit arch/i386/lib/cpu_reset.inc
66 ## Include an id string (For safe flashing)
68 mainboardinit arch/i386/lib/id.inc
69 ldscript /arch/i386/lib/id.lds
72 ### This is the early phase of coreboot startup
73 ### Things are delicate and we test to see if we should
74 ### failover to another image.
76 # if CONFIG_USE_FALLBACK_IMAGE
77 # ldscript /arch/i386/lib/failover.lds
78 # mainboardinit ./failover.inc
82 ### O.k. We aren't just an intermediary anymore!
88 mainboardinit cpu/x86/fpu/enable_fpu.inc
89 mainboardinit cpu/amd/model_gx1/cpu_setup.inc
90 mainboardinit cpu/amd/model_gx1/gx_setup.inc
91 mainboardinit ./auto.inc
94 ## Include the secondary Configuration files
99 chip northbridge/amd/gx1 # Northbridge
100 device pci_domain 0 on
101 device pci 0.0 on end # Host bridge
102 chip southbridge/amd/cs5530 # Southbridge
103 device pci 0f.0 off end # Ethernet (Realtek RTL8139B)
104 device pci 12.0 on # ISA bridge
105 chip superio/nsc/pc87351 # Super I/O
106 device pnp 2e.4 on # PS/2 keyboard (+ mouse?)
112 device pnp 2e.a on # PS/2 mouse
115 device pnp 2e.e on # COM1
119 device pnp 2e.f off # Floppy
124 device pnp 2e.10 on # Parallel port
128 device pnp 2e.12 on # COM2
134 device pci 12.1 off end # SMI
135 device pci 12.2 on end # IDE
136 device pci 12.3 on end # Audio
137 device pci 12.4 on end # VGA (onboard)
138 # device pci 12.4 on # VGA (onboard)
139 # chip drivers/pci/onboard
140 # device pci 12.4 on end
141 # register "rom_address" = "0xfffc0000" # 256 KB image
142 # # register "rom_address" = "0xfff80000" # 512 KB image
143 # # register "rom_address" = "0xfff00000" # 1 MB image
146 device pci 13.0 on end # USB
147 register "ide0_enable" = "1"
148 register "ide1_enable" = "1"
151 chip cpu/amd/model_gx1 # CPU