src/mainboard/amd/union_station/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* DefinitionBlock Statement */
  21 DefinitionBlock (
  22         "DSDT.AML",           /* Output filename */
  23         "DSDT",                 /* Signature */
  24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  25         "AMD   ",               /* OEMID */
  26         "UNIONSTN",          /* TABLE ID */
  27         0x00010001      /* OEM Revision */
  28         )
  29 {       /* Start of ASL file */
  30         /* #include <arch/i386/acpi/debug.asl> */               /* Include global debug methods if needed */
  31
  32         /* Data to be patched by the BIOS during POST */
  33         /* FIXME the patching is not done yet! */
  34         /* Memory related values */
  35         Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
  36         Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
  37         Name(PBLN, 0x0) /* Length of BIOS area */
  38
  39         Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)  /* Base address of PCIe config space */
  40         Name(HPBA, 0xFED00000)  /* Base address of HPET table */
  41
  42         Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
  43
  44         /* USB overcurrent mapping pins.   */
  45         Name(UOM0, 0)
  46         Name(UOM1, 2)
  47         Name(UOM2, 0)
  48         Name(UOM3, 7)
  49         Name(UOM4, 2)
  50         Name(UOM5, 2)
  51         Name(UOM6, 6)
  52         Name(UOM7, 2)
  53         Name(UOM8, 6)
  54         Name(UOM9, 6)
  55
  56         /* Some global data */
  57         Name(OSTP, 3)           /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
  58         Name(OSV, Ones) /* Assume nothing */
  59         Name(PMOD, One) /* Assume APIC */
  60
  61         /*
  62          * Processor Object
  63          *
  64          */
  65         Scope (\_PR) {          /* define processor scope */
  66                 Processor(
  67                         CPU0,           /* name space name */
  68                         0,              /* Unique number for this processor */
  69                         0x808,          /* PBLK system I/O address !hardcoded! */
  70                         0x06            /* PBLKLEN for boot processor */
  71                         ) {
  72                         #include "acpi/cpstate.asl"
  73                 }
  74
  75                 Processor(
  76                         CPU1,           /* name space name */
  77                         1,              /* Unique number for this processor */
  78                         0x0000,         /* PBLK system I/O address !hardcoded! */
  79                         0x00            /* PBLKLEN for boot processor */
  80                         ) {
  81                         #include "acpi/cpstate.asl"
  82                 }
  83         } /* End _PR scope */
  84
  85         /* PIC IRQ mapping registers, C00h-C01h. */
  86         OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
  87                 Field(PRQM, ByteAcc, NoLock, Preserve) {
  88                 PRQI, 0x00000008,
  89                 PRQD, 0x00000008,  /* Offset: 1h */
  90         }
  91         IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
  92                 PIRA, 0x00000008,       /* Index 0 */
  93                 PIRB, 0x00000008,       /* Index 1 */
  94                 PIRC, 0x00000008,       /* Index 2 */
  95                 PIRD, 0x00000008,       /* Index 3 */
  96                 PIRE, 0x00000008,       /* Index 4 */
  97                 PIRF, 0x00000008,       /* Index 5 */
  98                 PIRG, 0x00000008,       /* Index 6 */
  99                 PIRH, 0x00000008,       /* Index 7 */
 100         }
 101
 102         /* PCI Error control register */
 103         OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
 104                 Field(PERC, ByteAcc, NoLock, Preserve) {
 105                 SENS, 0x00000001,
 106                 PENS, 0x00000001,
 107                 SENE, 0x00000001,
 108                 PENE, 0x00000001,
 109         }
 110
 111         /* Client Management index/data registers */
 112         OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
 113                 Field(CMT, ByteAcc, NoLock, Preserve) {
 114                 CMTI,      8,
 115                 /* Client Management Data register */
 116                 G64E,   1,
 117                 G64O,      1,
 118                 G32O,      2,
 119                 ,       2,
 120                 GPSL,     2,
 121         }
 122
 123         /* GPM Port register */
 124         OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
 125                 Field(GPT, ByteAcc, NoLock, Preserve) {
 126                 GPB0,1,
 127                 GPB1,1,
 128                 GPB2,1,
 129                 GPB3,1,
 130                 GPB4,1,
 131                 GPB5,1,
 132                 GPB6,1,
 133                 GPB7,1,
 134         }
 135
 136         /* Flash ROM program enable register */
 137         OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
 138                 Field(FRE, ByteAcc, NoLock, Preserve) {
 139                 ,     0x00000006,
 140                 FLRE, 0x00000001,
 141         }
 142
 143         /* PM2 index/data registers */
 144         OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
 145                 Field(PM2R, ByteAcc, NoLock, Preserve) {
 146                 PM2I, 0x00000008,
 147                 PM2D, 0x00000008,
 148         }
 149
 150         /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
 151         OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
 152                 Field(PIOR, ByteAcc, NoLock, Preserve) {
 153                 PIOI, 0x00000008,
 154                 PIOD, 0x00000008,
 155         }
 156         IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 157                 Offset(0x00),   /* MiscControl */
 158                 , 1,
 159                 T1EE, 1,
 160                 T2EE, 1,
 161                 Offset(0x01),   /* MiscStatus */
 162                 , 1,
 163                 T1E, 1,
 164                 T2E, 1,
 165                 Offset(0x04),   /* SmiWakeUpEventEnable3 */
 166                 , 7,
 167                 SSEN, 1,
 168                 Offset(0x07),   /* SmiWakeUpEventStatus3 */
 169                 , 7,
 170                 CSSM, 1,
 171                 Offset(0x10),   /* AcpiEnable */
 172                 , 6,
 173                 PWDE, 1,
 174                 Offset(0x1C),   /* ProgramIoEnable */
 175                 , 3,
 176                 MKME, 1,
 177                 IO3E, 1,
 178                 IO2E, 1,
 179                 IO1E, 1,
 180                 IO0E, 1,
 181                 Offset(0x1D),   /* IOMonitorStatus */
 182                 , 3,
 183                 MKMS, 1,
 184                 IO3S, 1,
 185                 IO2S, 1,
 186                 IO1S, 1,
 187                 IO0S,1,
 188                 Offset(0x20),   /* AcpiPmEvtBlk. TODO: should be 0x60 */
 189                 APEB, 16,
 190                 Offset(0x36),   /* GEvtLevelConfig */
 191                 , 6,
 192                 ELC6, 1,
 193                 ELC7, 1,
 194                 Offset(0x37),   /* GPMLevelConfig0 */
 195                 , 3,
 196                 PLC0, 1,
 197                 PLC1, 1,
 198                 PLC2, 1,
 199                 PLC3, 1,
 200                 PLC8, 1,
 201                 Offset(0x38),   /* GPMLevelConfig1 */
 202                 , 1,
 203                  PLC4, 1,
 204                  PLC5, 1,
 205                 , 1,
 206                  PLC6, 1,
 207                  PLC7, 1,
 208                 Offset(0x3B),   /* PMEStatus1 */
 209                 GP0S, 1,
 210                 GM4S, 1,
 211                 GM5S, 1,
 212                 APS, 1,
 213                 GM6S, 1,
 214                 GM7S, 1,
 215                 GP2S, 1,
 216                 STSS, 1,
 217                 Offset(0x55),   /* SoftPciRst */
 218                 SPRE, 1,
 219                 , 1,
 220                 , 1,
 221                 PNAT, 1,
 222                 PWMK, 1,
 223                 PWNS, 1,
 224
 225                 /*      Offset(0x61), */        /*  Options_1 */
 226                 /*              ,7,  */
 227                 /*              R617,1, */
 228
 229                 Offset(0x65),   /* UsbPMControl */
 230                 , 4,
 231                 URRE, 1,
 232                 Offset(0x68),   /* MiscEnable68 */
 233                 , 3,
 234                 TMTE, 1,
 235                 , 1,
 236                 Offset(0x92),   /* GEVENTIN */
 237                 , 7,
 238                 E7IS, 1,
 239                 Offset(0x96),   /* GPM98IN */
 240                 G8IS, 1,
 241                 G9IS, 1,
 242                 Offset(0x9A),   /* EnhanceControl */
 243                 ,7,
 244                 HPDE, 1,
 245                 Offset(0xA8),   /* PIO7654Enable */
 246                 IO4E, 1,
 247                 IO5E, 1,
 248                 IO6E, 1,
 249                 IO7E, 1,
 250                 Offset(0xA9),   /* PIO7654Status */
 251                 IO4S, 1,
 252                 IO5S, 1,
 253                 IO6S, 1,
 254                 IO7S, 1,
 255         }
 256
 257         /* PM1 Event Block
 258         * First word is PM1_Status, Second word is PM1_Enable
 259         */
 260         OperationRegion(P1EB, SystemIO, APEB, 0x04)
 261                 Field(P1EB, ByteAcc, NoLock, Preserve) {
 262                 TMST, 1,
 263                 ,    3,
 264                 BMST,    1,
 265                 GBST,   1,
 266                 Offset(0x01),
 267                 PBST, 1,
 268                 , 1,
 269                 RTST, 1,
 270                 , 3,
 271                 PWST, 1,
 272                 SPWS, 1,
 273                 Offset(0x02),
 274                 TMEN, 1,
 275                 , 4,
 276                 GBEN, 1,
 277                 Offset(0x03),
 278                 PBEN, 1,
 279                 , 1,
 280                 RTEN, 1,
 281                 , 3,
 282                 PWDA, 1,
 283         }
 284
 285         Scope(\_SB) {
 286                 /* PCIe Configuration Space for 16 busses */
 287                 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
 288                         Field(PCFG, ByteAcc, NoLock, Preserve) {
 289                         /* Byte offsets are computed using the following technique:
 290                          * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 291                          * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 292                         */
 293                         Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
 294                         STB5, 32,
 295                         Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 296                         PT0D, 1,
 297                         PT1D, 1,
 298                         PT2D, 1,
 299                         PT3D, 1,
 300                         PT4D, 1,
 301                         PT5D, 1,
 302                         PT6D, 1,
 303                         PT7D, 1,
 304                         PT8D, 1,
 305                         PT9D, 1,
 306                         Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
 307                         SBIE, 1,
 308                         SBME, 1,
 309                         Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
 310                         SBRI, 8,
 311                         Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
 312                         SBB1, 32,
 313                         Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
 314                         ,14,
 315                         P92E, 1,                /* Port92 decode enable */
 316                 }
 317
 318                 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
 319                         Field(SB5, AnyAcc, NoLock, Preserve){
 320                         /* Port 0 */
 321                         Offset(0x120),          /* Port 0 Task file status */
 322                         P0ER, 1,
 323                         , 2,
 324                         P0DQ, 1,
 325                         , 3,
 326                         P0BY, 1,
 327                         Offset(0x128),          /* Port 0 Serial ATA status */
 328                         P0DD, 4,
 329                         , 4,
 330                         P0IS, 4,
 331                         Offset(0x12C),          /* Port 0 Serial ATA control */
 332                         P0DI, 4,
 333                         Offset(0x130),          /* Port 0 Serial ATA error */
 334                         , 16,
 335                         P0PR, 1,
 336
 337                         /* Port 1 */
 338                         offset(0x1A0),          /* Port 1 Task file status */
 339                         P1ER, 1,
 340                         , 2,
 341                         P1DQ, 1,
 342                         , 3,
 343                         P1BY, 1,
 344                         Offset(0x1A8),          /* Port 1 Serial ATA status */
 345                         P1DD, 4,
 346                         , 4,
 347                         P1IS, 4,
 348                         Offset(0x1AC),          /* Port 1 Serial ATA control */
 349                         P1DI, 4,
 350                         Offset(0x1B0),          /* Port 1 Serial ATA error */
 351                         , 16,
 352                         P1PR, 1,
 353
 354                         /* Port 2 */
 355                         Offset(0x220),          /* Port 2 Task file status */
 356                         P2ER, 1,
 357                         , 2,
 358                         P2DQ, 1,
 359                         , 3,
 360                         P2BY, 1,
 361                         Offset(0x228),          /* Port 2 Serial ATA status */
 362                         P2DD, 4,
 363                         , 4,
 364                         P2IS, 4,
 365                         Offset(0x22C),          /* Port 2 Serial ATA control */
 366                         P2DI, 4,
 367                         Offset(0x230),          /* Port 2 Serial ATA error */
 368                         , 16,
 369                         P2PR, 1,
 370
 371                         /* Port 3 */
 372                         Offset(0x2A0),          /* Port 3 Task file status */
 373                         P3ER, 1,
 374                         , 2,
 375                         P3DQ, 1,
 376                         , 3,
 377                         P3BY, 1,
 378                         Offset(0x2A8),          /* Port 3 Serial ATA status */
 379                         P3DD, 4,
 380                         , 4,
 381                         P3IS, 4,
 382                         Offset(0x2AC),          /* Port 3 Serial ATA control */
 383                         P3DI, 4,
 384                         Offset(0x2B0),          /* Port 3 Serial ATA error */
 385                         , 16,
 386                         P3PR, 1,
 387                 }
 388         }
 389
 390
 391         #include "acpi/routing.asl"
 392
 393         Scope(\_SB) {
 394
 395                 Method(CkOT, 0){
 396
 397                         if(LNotEqual(OSTP, Ones)) {Return(OSTP)}        /* OS version was already detected */
 398
 399                         if(CondRefOf(\_OSI,Local1))
 400                         {
 401                                 Store(1, OSTP)                /* Assume some form of XP */
 402                                 if (\_OSI("Windows 2006"))      /* Vista */
 403                                 {
 404                                         Store(2, OSTP)
 405                                 }
 406                         } else {
 407                                 If(WCMP(\_OS,"Linux")) {
 408                                         Store(3, OSTP)            /* Linux */
 409                                 } Else {
 410                                         Store(4, OSTP)            /* Gotta be WinCE */
 411                                 }
 412                         }
 413                         Return(OSTP)
 414                 }
 415
 416                 Method(_PIC, 0x01, NotSerialized)
 417                 {
 418                         If (Arg0)
 419                         {
 420                                 \_SB.CIRQ()
 421                         }
 422                         Store(Arg0, PMOD)
 423                 }
 424                 Method(CIRQ, 0x00, NotSerialized){
 425                         Store(0, PIRA)
 426                         Store(0, PIRB)
 427                         Store(0, PIRC)
 428                         Store(0, PIRD)
 429                         Store(0, PIRE)
 430                         Store(0, PIRF)
 431                         Store(0, PIRG)
 432                         Store(0, PIRH)
 433                 }
 434
 435                 Name(IRQB, ResourceTemplate(){
 436                         IRQ(Level,ActiveLow,Shared){15}
 437                 })
 438
 439                 Name(IRQP, ResourceTemplate(){
 440                         IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
 441                 })
 442
 443                 Name(PITF, ResourceTemplate(){
 444                         IRQ(Level,ActiveLow,Exclusive){9}
 445                 })
 446
 447                 Device(INTA) {
 448                         Name(_HID, EISAID("PNP0C0F"))
 449                         Name(_UID, 1)
 450
 451                         Method(_STA, 0) {
 452                                 if (PIRA) {
 453                                         Return(0x0B) /* sata is invisible */
 454                                 } else {
 455                                         Return(0x09) /* sata is disabled */
 456                                 }
 457                         } /* End Method(_SB.INTA._STA) */
 458
 459                         Method(_DIS ,0) {
 460                                 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
 461                                 Store(0, PIRA)
 462                         } /* End Method(_SB.INTA._DIS) */
 463
 464                         Method(_PRS ,0) {
 465                                 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
 466                                 Return(IRQP)
 467                         } /* Method(_SB.INTA._PRS) */
 468
 469                         Method(_CRS ,0) {
 470                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 471                                 CreateWordField(IRQB, 0x1, IRQN)
 472                                 ShiftLeft(1, PIRA, IRQN)
 473                                 Return(IRQB)
 474                         } /* Method(_SB.INTA._CRS) */
 475
 476                         Method(_SRS, 1) {
 477                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
 478                                 CreateWordField(ARG0, 1, IRQM)
 479
 480                                 /* Use lowest available IRQ */
 481                                 FindSetRightBit(IRQM, Local0)
 482                                 if (Local0) {
 483                                         Decrement(Local0)
 484                                 }
 485                                 Store(Local0, PIRA)
 486                         } /* End Method(_SB.INTA._SRS) */
 487                 } /* End Device(INTA) */
 488
 489                 Device(INTB) {
 490                         Name(_HID, EISAID("PNP0C0F"))
 491                         Name(_UID, 2)
 492
 493                         Method(_STA, 0) {
 494                                 if (PIRB) {
 495                                         Return(0x0B) /* sata is invisible */
 496                                 } else {
 497                                         Return(0x09) /* sata is disabled */
 498                                 }
 499                         } /* End Method(_SB.INTB._STA) */
 500
 501                         Method(_DIS ,0) {
 502                                 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
 503                                 Store(0, PIRB)
 504                         } /* End Method(_SB.INTB._DIS) */
 505
 506                         Method(_PRS ,0) {
 507                                 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
 508                                 Return(IRQP)
 509                         } /* Method(_SB.INTB._PRS) */
 510
 511                         Method(_CRS ,0) {
 512                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 513                                 CreateWordField(IRQB, 0x1, IRQN)
 514                                 ShiftLeft(1, PIRB, IRQN)
 515                                 Return(IRQB)
 516                         } /* Method(_SB.INTB._CRS) */
 517
 518                         Method(_SRS, 1) {
 519                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
 520                                 CreateWordField(ARG0, 1, IRQM)
 521
 522                                 /* Use lowest available IRQ */
 523                                 FindSetRightBit(IRQM, Local0)
 524                                 if (Local0) {
 525                                         Decrement(Local0)
 526                                 }
 527                                 Store(Local0, PIRB)
 528                         } /* End Method(_SB.INTB._SRS) */
 529                 } /* End Device(INTB)  */
 530
 531                 Device(INTC) {
 532                         Name(_HID, EISAID("PNP0C0F"))
 533                         Name(_UID, 3)
 534
 535                         Method(_STA, 0) {
 536                                 if (PIRC) {
 537                                         Return(0x0B) /* sata is invisible */
 538                                 } else {
 539                                         Return(0x09) /* sata is disabled */
 540                                 }
 541                         } /* End Method(_SB.INTC._STA) */
 542
 543                         Method(_DIS ,0) {
 544                                 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
 545                                 Store(0, PIRC)
 546                         } /* End Method(_SB.INTC._DIS) */
 547
 548                         Method(_PRS ,0) {
 549                                 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
 550                                 Return(IRQP)
 551                         } /* Method(_SB.INTC._PRS) */
 552
 553                         Method(_CRS ,0) {
 554                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 555                                 CreateWordField(IRQB, 0x1, IRQN)
 556                                 ShiftLeft(1, PIRC, IRQN)
 557                                 Return(IRQB)
 558                         } /* Method(_SB.INTC._CRS) */
 559
 560                         Method(_SRS, 1) {
 561                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
 562                                 CreateWordField(ARG0, 1, IRQM)
 563
 564                                 /* Use lowest available IRQ */
 565                                 FindSetRightBit(IRQM, Local0)
 566                                 if (Local0) {
 567                                         Decrement(Local0)
 568                                 }
 569                                 Store(Local0, PIRC)
 570                         } /* End Method(_SB.INTC._SRS) */
 571                 } /* End Device(INTC)  */
 572
 573                 Device(INTD) {
 574                         Name(_HID, EISAID("PNP0C0F"))
 575                         Name(_UID, 4)
 576
 577                         Method(_STA, 0) {
 578                                 if (PIRD) {
 579                                         Return(0x0B) /* sata is invisible */
 580                                 } else {
 581                                         Return(0x09) /* sata is disabled */
 582                                 }
 583                         } /* End Method(_SB.INTD._STA) */
 584
 585                         Method(_DIS ,0) {
 586                                 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
 587                                 Store(0, PIRD)
 588                         } /* End Method(_SB.INTD._DIS) */
 589
 590                         Method(_PRS ,0) {
 591                                 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
 592                                 Return(IRQP)
 593                         } /* Method(_SB.INTD._PRS) */
 594
 595                         Method(_CRS ,0) {
 596                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 597                                 CreateWordField(IRQB, 0x1, IRQN)
 598                                 ShiftLeft(1, PIRD, IRQN)
 599                                 Return(IRQB)
 600                         } /* Method(_SB.INTD._CRS) */
 601
 602                         Method(_SRS, 1) {
 603                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
 604                                 CreateWordField(ARG0, 1, IRQM)
 605
 606                                 /* Use lowest available IRQ */
 607                                 FindSetRightBit(IRQM, Local0)
 608                                 if (Local0) {
 609                                         Decrement(Local0)
 610                                 }
 611                                 Store(Local0, PIRD)
 612                         } /* End Method(_SB.INTD._SRS) */
 613                 } /* End Device(INTD)  */
 614
 615                 Device(INTE) {
 616                         Name(_HID, EISAID("PNP0C0F"))
 617                         Name(_UID, 5)
 618
 619                         Method(_STA, 0) {
 620                                 if (PIRE) {
 621                                         Return(0x0B) /* sata is invisible */
 622                                 } else {
 623                                         Return(0x09) /* sata is disabled */
 624                                 }
 625                         } /* End Method(_SB.INTE._STA) */
 626
 627                         Method(_DIS ,0) {
 628                                 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
 629                                 Store(0, PIRE)
 630                         } /* End Method(_SB.INTE._DIS) */
 631
 632                         Method(_PRS ,0) {
 633                                 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
 634                                 Return(IRQP)
 635                         } /* Method(_SB.INTE._PRS) */
 636
 637                         Method(_CRS ,0) {
 638                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 639                                 CreateWordField(IRQB, 0x1, IRQN)
 640                                 ShiftLeft(1, PIRE, IRQN)
 641                                 Return(IRQB)
 642                         } /* Method(_SB.INTE._CRS) */
 643
 644                         Method(_SRS, 1) {
 645                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
 646                                 CreateWordField(ARG0, 1, IRQM)
 647
 648                                 /* Use lowest available IRQ */
 649                                 FindSetRightBit(IRQM, Local0)
 650                                 if (Local0) {
 651                                         Decrement(Local0)
 652                                 }
 653                                 Store(Local0, PIRE)
 654                         } /* End Method(_SB.INTE._SRS) */
 655                 } /* End Device(INTE)  */
 656
 657                 Device(INTF) {
 658                         Name(_HID, EISAID("PNP0C0F"))
 659                         Name(_UID, 6)
 660
 661                         Method(_STA, 0) {
 662                                 if (PIRF) {
 663                                         Return(0x0B) /* sata is invisible */
 664                                 } else {
 665                                         Return(0x09) /* sata is disabled */
 666                                 }
 667                         } /* End Method(_SB.INTF._STA) */
 668
 669                         Method(_DIS ,0) {
 670                                 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
 671                                 Store(0, PIRF)
 672                         } /* End Method(_SB.INTF._DIS) */
 673
 674                         Method(_PRS ,0) {
 675                                 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
 676                                 Return(PITF)
 677                         } /* Method(_SB.INTF._PRS) */
 678
 679                         Method(_CRS ,0) {
 680                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 681                                 CreateWordField(IRQB, 0x1, IRQN)
 682                                 ShiftLeft(1, PIRF, IRQN)
 683                                 Return(IRQB)
 684                         } /* Method(_SB.INTF._CRS) */
 685
 686                         Method(_SRS, 1) {
 687                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
 688                                 CreateWordField(ARG0, 1, IRQM)
 689
 690                                 /* Use lowest available IRQ */
 691                                 FindSetRightBit(IRQM, Local0)
 692                                 if (Local0) {
 693                                         Decrement(Local0)
 694                                 }
 695                                 Store(Local0, PIRF)
 696                         } /*  End Method(_SB.INTF._SRS) */
 697                 } /* End Device(INTF)  */
 698
 699                 Device(INTG) {
 700                         Name(_HID, EISAID("PNP0C0F"))
 701                         Name(_UID, 7)
 702
 703                         Method(_STA, 0) {
 704                                 if (PIRG) {
 705                                         Return(0x0B) /* sata is invisible */
 706                                 } else {
 707                                         Return(0x09) /* sata is disabled */
 708                                 }
 709                         } /* End Method(_SB.INTG._STA)  */
 710
 711                         Method(_DIS ,0) {
 712                                 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
 713                                 Store(0, PIRG)
 714                         } /* End Method(_SB.INTG._DIS)  */
 715
 716                         Method(_PRS ,0) {
 717                                 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
 718                                 Return(IRQP)
 719                         } /* Method(_SB.INTG._CRS)  */
 720
 721                         Method(_CRS ,0) {
 722                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 723                                 CreateWordField(IRQB, 0x1, IRQN)
 724                                 ShiftLeft(1, PIRG, IRQN)
 725                                 Return(IRQB)
 726                         } /* Method(_SB.INTG._CRS)  */
 727
 728                         Method(_SRS, 1) {
 729                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
 730                                 CreateWordField(ARG0, 1, IRQM)
 731
 732                                 /* Use lowest available IRQ */
 733                                 FindSetRightBit(IRQM, Local0)
 734                                 if (Local0) {
 735                                         Decrement(Local0)
 736                                 }
 737                                 Store(Local0, PIRG)
 738                         } /* End Method(_SB.INTG._SRS)  */
 739                 } /* End Device(INTG)  */
 740
 741                 Device(INTH) {
 742                         Name(_HID, EISAID("PNP0C0F"))
 743                         Name(_UID, 8)
 744
 745                         Method(_STA, 0) {
 746                                 if (PIRH) {
 747                                         Return(0x0B) /* sata is invisible */
 748                                 } else {
 749                                         Return(0x09) /* sata is disabled */
 750                                 }
 751                         } /* End Method(_SB.INTH._STA)  */
 752
 753                         Method(_DIS ,0) {
 754                                 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
 755                                 Store(0, PIRH)
 756                         } /* End Method(_SB.INTH._DIS)  */
 757
 758                         Method(_PRS ,0) {
 759                                 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
 760                                 Return(IRQP)
 761                         } /* Method(_SB.INTH._CRS)  */
 762
 763                         Method(_CRS ,0) {
 764                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 765                                 CreateWordField(IRQB, 0x1, IRQN)
 766                                 ShiftLeft(1, PIRH, IRQN)
 767                                 Return(IRQB)
 768                         } /* Method(_SB.INTH._CRS)  */
 769
 770                         Method(_SRS, 1) {
 771                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
 772                                 CreateWordField(ARG0, 1, IRQM)
 773
 774                                 /* Use lowest available IRQ */
 775                                 FindSetRightBit(IRQM, Local0)
 776                                 if (Local0) {
 777                                         Decrement(Local0)
 778                                 }
 779                                 Store(Local0, PIRH)
 780                         } /* End Method(_SB.INTH._SRS)  */
 781                 } /* End Device(INTH)   */
 782
 783         }   /* End Scope(_SB)  */
 784
 785
 786         /* Supported sleep states: */
 787         Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
 788
 789         If (LAnd(SSFG, 0x01)) {
 790                 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
 791         }
 792         If (LAnd(SSFG, 0x02)) {
 793                 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
 794         }
 795         If (LAnd(SSFG, 0x04)) {
 796                 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
 797         }
 798         If (LAnd(SSFG, 0x08)) {
 799                 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
 800         }
 801
 802         Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
 803
 804         Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
 805         Name(CSMS, 0)                   /* Current System State */
 806
 807         /* Wake status package */
 808         Name(WKST,Package(){Zero, Zero})
 809
 810         /*
 811         * \_PTS - Prepare to Sleep method
 812         *
 813         *       Entry:
 814         *               Arg0=The value of the sleeping state S1=1, S2=2, etc
 815         *
 816         * Exit:
 817         *               -none-
 818         *
 819         * The _PTS control method is executed at the beginning of the sleep process
 820         * for S1-S5. The sleeping value is passed to the _PTS control method.   This
 821         * control method may be executed a relatively long time before entering the
 822         * sleep state and the OS may abort      the operation without notification to
 823         * the ACPI driver.  This method cannot modify the configuration or power
 824         * state of any device in the system.
 825         */
 826         Method(\_PTS, 1) {
 827                 /* DBGO("\\_PTS\n") */
 828                 /* DBGO("From S0 to S") */
 829                 /* DBGO(Arg0) */
 830                 /* DBGO("\n") */
 831
 832                 /* Don't allow PCIRST# to reset USB */
 833                 if (LEqual(Arg0,3)){
 834                         Store(0,URRE)
 835                 }
 836
 837                 /* Clear sleep SMI status flag and enable sleep SMI trap. */
 838                 /*Store(One, CSSM)
 839                 Store(One, SSEN)*/
 840
 841                 /* On older chips, clear PciExpWakeDisEn */
 842                 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
 843                 *       Store(0,\_SB.PWDE)
 844                 *}
 845                 */
 846
 847                 /* Clear wake status structure. */
 848                 Store(0, Index(WKST,0))
 849                 Store(0, Index(WKST,1))
 850         } /* End Method(\_PTS) */
 851
 852         /*
 853         *  The following method results in a "not a valid reserved NameSeg"
 854         *  warning so I have commented it out for the duration.  It isn't
 855         *  used, so it could be removed.
 856         *
 857         *
 858         *       \_GTS OEM Going To Sleep method
 859         *
 860         *       Entry:
 861         *               Arg0=The value of the sleeping state S1=1, S2=2
 862         *
 863         *       Exit:
 864         *               -none-
 865         *
 866         *  Method(\_GTS, 1) {
 867         *  DBGO("\\_GTS\n")
 868         *  DBGO("From S0 to S")
 869         *  DBGO(Arg0)
 870         *  DBGO("\n")
 871         *  }
 872         */
 873
 874         /*
 875         *       \_BFS OEM Back From Sleep method
 876         *
 877         *       Entry:
 878         *               Arg0=The value of the sleeping state S1=1, S2=2
 879         *
 880         *       Exit:
 881         *               -none-
 882         */
 883         Method(\_BFS, 1) {
 884                 /* DBGO("\\_BFS\n") */
 885                 /* DBGO("From S") */
 886                 /* DBGO(Arg0) */
 887                 /* DBGO(" to S0\n") */
 888         }
 889
 890         /*
 891         *  \_WAK System Wake method
 892         *
 893         *       Entry:
 894         *               Arg0=The value of the sleeping state S1=1, S2=2
 895         *
 896         *       Exit:
 897         *               Return package of 2 DWords
 898         *               Dword 1 - Status
 899         *                       0x00000000      wake succeeded
 900         *                       0x00000001      Wake was signaled but failed due to lack of power
 901         *                       0x00000002      Wake was signaled but failed due to thermal condition
 902         *               Dword 2 - Power Supply state
 903         *                       if non-zero the effective S-state the power supply entered
 904         */
 905         Method(\_WAK, 1) {
 906                 /* DBGO("\\_WAK\n") */
 907                 /* DBGO("From S") */
 908                 /* DBGO(Arg0) */
 909                 /* DBGO(" to S0\n") */
 910
 911                 /* Re-enable HPET */
 912                 Store(1,HPDE)
 913
 914                 /* Restore PCIRST# so it resets USB */
 915                 if (LEqual(Arg0,3)){
 916                         Store(1,URRE)
 917                 }
 918
 919                 /* Arbitrarily clear PciExpWakeStatus */
 920                 Store(PWST, PWST)
 921
 922                 /* if(DeRefOf(Index(WKST,0))) {
 923                 *       Store(0, Index(WKST,1))
 924                 * } else {
 925                 *       Store(Arg0, Index(WKST,1))
 926                 * }
 927                 */
 928                 Return(WKST)
 929         } /* End Method(\_WAK) */
 930
 931         Scope(\_GPE) {  /* Start Scope GPE */
 932                 /*  General event 0  */
 933                 /* Method(_L00) {
 934                 *       DBGO("\\_GPE\\_L00\n")
 935                 * }
 936                 */
 937
 938                 /*  General event 1  */
 939                 /* Method(_L01) {
 940                 *       DBGO("\\_GPE\\_L00\n")
 941                 * }
 942                 */
 943
 944                 /*  General event 2  */
 945                 /* Method(_L02) {
 946                 *       DBGO("\\_GPE\\_L00\n")
 947                 * }
 948                 */
 949
 950                 /*  General event 3  */
 951                 Method(_L03) {
 952                         /* DBGO("\\_GPE\\_L00\n") */
 953                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 954                 }
 955
 956                 /*  General event 4  */
 957                 /* Method(_L04) {
 958                 *       DBGO("\\_GPE\\_L00\n")
 959                 * }
 960                 */
 961
 962                 /*  General event 5  */
 963                 /* Method(_L05) {
 964                 *       DBGO("\\_GPE\\_L00\n")
 965                 * }
 966                 */
 967
 968                 /*  General event 6 - Used for GPM6, moved to USB.asl */
 969                 /* Method(_L06) {
 970                 *       DBGO("\\_GPE\\_L00\n")
 971                 * }
 972                 */
 973
 974                 /*  General event 7 - Used for GPM7, moved to USB.asl */
 975                 /* Method(_L07) {
 976                 *       DBGO("\\_GPE\\_L07\n")
 977                 * }
 978                 */
 979
 980                 /*  Legacy PM event  */
 981                 Method(_L08) {
 982                         /* DBGO("\\_GPE\\_L08\n") */
 983                 }
 984
 985                 /*  Temp warning (TWarn) event  */
 986                 Method(_L09) {
 987                         /* DBGO("\\_GPE\\_L09\n") */
 988                         /* Notify (\_TZ.TZ00, 0x80) */
 989                 }
 990
 991                 /*  Reserved  */
 992                 /* Method(_L0A) {
 993                 *       DBGO("\\_GPE\\_L0A\n")
 994                 * }
 995                 */
 996
 997                 /*  USB controller PME#  */
 998                 Method(_L0B) {
 999                         /* DBGO("\\_GPE\\_L0B\n") */
1000                         Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1001                         Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1002                         Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1003                         Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1004                         Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1005                         Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
1006                         Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1007                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1008                 }
1009
1010                 /*  AC97 controller PME#  */
1011                 /* Method(_L0C) {
1012                 *       DBGO("\\_GPE\\_L0C\n")
1013                 * }
1014                 */
1015
1016                 /*  OtherTherm PME#  */
1017                 /* Method(_L0D) {
1018                 *       DBGO("\\_GPE\\_L0D\n")
1019                 * }
1020                 */
1021
1022                 /*  GPM9 SCI event - Moved to USB.asl */
1023                 /* Method(_L0E) {
1024                 *       DBGO("\\_GPE\\_L0E\n")
1025                 * }
1026                 */
1027
1028                 /*  PCIe HotPlug event  */
1029                 /* Method(_L0F) {
1030                 *       DBGO("\\_GPE\\_L0F\n")
1031                 * }
1032                 */
1033
1034                 /*  ExtEvent0 SCI event  */
1035                 Method(_L10) {
1036                         /* DBGO("\\_GPE\\_L10\n") */
1037                 }
1038
1039
1040                 /*  ExtEvent1 SCI event  */
1041                 Method(_L11) {
1042                         /* DBGO("\\_GPE\\_L11\n") */
1043                 }
1044
1045                 /*  PCIe PME# event  */
1046                 /* Method(_L12) {
1047                 *       DBGO("\\_GPE\\_L12\n")
1048                 * }
1049                 */
1050
1051                 /*  GPM0 SCI event - Moved to USB.asl */
1052                 /* Method(_L13) {
1053                 *       DBGO("\\_GPE\\_L13\n")
1054                 * }
1055                 */
1056
1057                 /*  GPM1 SCI event - Moved to USB.asl */
1058                 /* Method(_L14) {
1059                 *       DBGO("\\_GPE\\_L14\n")
1060                 * }
1061                 */
1062
1063                 /*  GPM2 SCI event - Moved to USB.asl */
1064                 /* Method(_L15) {
1065                 *       DBGO("\\_GPE\\_L15\n")
1066                 * }
1067                 */
1068
1069                 /*  GPM3 SCI event - Moved to USB.asl */
1070                 /* Method(_L16) {
1071                 *       DBGO("\\_GPE\\_L16\n")
1072                 * }
1073                 */
1074
1075                 /*  GPM8 SCI event - Moved to USB.asl */
1076                 /* Method(_L17) {
1077                 *       DBGO("\\_GPE\\_L17\n")
1078                 * }
1079                 */
1080
1081                 /*  GPIO0 or GEvent8 event  */
1082                 Method(_L18) {
1083                         /* DBGO("\\_GPE\\_L18\n") */
1084                         Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1085                         Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1086                         Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1087                         Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1088                         Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1089                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1090                 }
1091
1092                 /*  GPM4 SCI event - Moved to USB.asl */
1093                 /* Method(_L19) {
1094                 *       DBGO("\\_GPE\\_L19\n")
1095                 * }
1096                 */
1097
1098                 /*  GPM5 SCI event - Moved to USB.asl */
1099                 /* Method(_L1A) {
1100                 *       DBGO("\\_GPE\\_L1A\n")
1101                 * }
1102                 */
1103
1104                 /*  Azalia SCI event  */
1105                 Method(_L1B) {
1106                         /* DBGO("\\_GPE\\_L1B\n") */
1107                         Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1108                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1109                 }
1110
1111                 /*  GPM6 SCI event - Reassigned to _L06 */
1112                 /* Method(_L1C) {
1113                 *       DBGO("\\_GPE\\_L1C\n")
1114                 * }
1115                 */
1116
1117                 /*  GPM7 SCI event - Reassigned to _L07 */
1118                 /* Method(_L1D) {
1119                 *       DBGO("\\_GPE\\_L1D\n")
1120                 * }
1121                 */
1122
1123                 /*  GPIO2 or GPIO66 SCI event  */
1124                 /* Method(_L1E) {
1125                 *       DBGO("\\_GPE\\_L1E\n")
1126                 * }
1127                 */
1128
1129                 /*  SATA SCI event - Moved to sata.asl */
1130                 /* Method(_L1F) {
1131                 *        DBGO("\\_GPE\\_L1F\n")
1132                 * }
1133                 */
1134
1135         }       /* End Scope GPE */
1136
1137         #include "acpi/usb.asl"
1138
1139         /* South Bridge */
1140         Scope(\_SB) { /* Start \_SB scope */
1141                 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1142
1143                 /*  _SB.PCI0 */
1144                 /* Note: Only need HID on Primary Bus */
1145                 Device(PCI0) {
1146                         External (TOM1)
1147                         External (TOM2)
1148                         Name(_HID, EISAID("PNP0A03"))
1149                         Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
1150                         Method(_BBN, 0) { /* Bus number = 0 */
1151                                 Return(0)
1152                         }
1153                         Method(_STA, 0) {
1154                                 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1155                                 Return(0x0B)     /* Status is visible */
1156                         }
1157
1158                         Method(_PRT,0) {
1159                                 If(PMOD){ Return(APR0) }   /* APIC mode */
1160                                 Return (PR0)                  /* PIC Mode */
1161                         } /* end _PRT */
1162
1163                         /* Describe the Northbridge devices */
1164                         Device(AMRT) {
1165                                 Name(_ADR, 0x00000000)
1166                         } /* end AMRT */
1167
1168                         /* The internal GFX bridge */
1169                         Device(HDMI) {
1170                                 Name(_ADR, 0x00010000)
1171                                 Name(_PRW, Package() {0x18, 4})
1172                                 Method(_PRT,0) {
1173                                         If(PMOD){ Return(APR1) }   /* APIC mode */
1174                                         Return (PR1)                  /* PIC Mode */
1175                                 }
1176                         }  /* end HDMI */
1177
1178                         /* The external GFX bridge */
1179                         Device(PBR2) {
1180                                 Name(_ADR, 0x00020000)
1181                                 Name(_PRW, Package() {0x18, 4})
1182                                 Method(_PRT,0) {
1183                                         If(PMOD){ Return(APS2) }   /* APIC mode */
1184                                         Return (PS2)                  /* PIC Mode */
1185                                 } /* end _PRT */
1186                         } /* end PBR2 */
1187
1188                         /* Dev3 is also an external GFX bridge, not used in Herring */
1189
1190                         Device(PBR4) {
1191                                 Name(_ADR, 0x00040000)
1192                                 Name(_PRW, Package() {0x18, 4})
1193                                 Method(_PRT,0) {
1194                                         If(PMOD){ Return(APS4) }   /* APIC mode */
1195                                         Return (PS4)                  /* PIC Mode */
1196                                 } /* end _PRT */
1197                         } /* end PBR4 */
1198
1199                         Device(PBR5) {
1200                                 Name(_ADR, 0x00050000)
1201                                 Name(_PRW, Package() {0x18, 4})
1202                                 Method(_PRT,0) {
1203                                         If(PMOD){ Return(APS5) }   /* APIC mode */
1204                                         Return (PS5)                  /* PIC Mode */
1205                                 } /* end _PRT */
1206                         } /* end PBR5 */
1207
1208                         Device(PBR6) {
1209                                 Name(_ADR, 0x00060000)
1210                                 Name(_PRW, Package() {0x18, 4})
1211                                 Method(_PRT,0) {
1212                                         If(PMOD){ Return(APS6) }   /* APIC mode */
1213                                         Return (PS6)                  /* PIC Mode */
1214                                 } /* end _PRT */
1215                         } /* end PBR6 */
1216
1217                         /* The onboard EtherNet chip */
1218                         Device(PBR7) {
1219                                 Name(_ADR, 0x00070000)
1220                                 Name(_PRW, Package() {0x18, 4})
1221                                 Method(_PRT,0) {
1222                                         If(PMOD){ Return(APS7) }   /* APIC mode */
1223                                         Return (PS7)                  /* PIC Mode */
1224                                 } /* end _PRT */
1225                         } /* end PBR7 */
1226
1227                         /* GPP */
1228                         Device(PBR9) {
1229                                 Name(_ADR, 0x00090000)
1230                                 Name(_PRW, Package() {0x18, 4})
1231                                 Method(_PRT,0) {
1232                                         If(PMOD){ Return(APS9) }   /* APIC mode */
1233                                         Return (PS9)                  /* PIC Mode */
1234                                 } /* end _PRT */
1235                         } /* end PBR9 */
1236
1237                         Device(PBRa) {
1238                                 Name(_ADR, 0x000A0000)
1239                                 Name(_PRW, Package() {0x18, 4})
1240                                 Method(_PRT,0) {
1241                                         If(PMOD){ Return(APSa) }   /* APIC mode */
1242                                         Return (PSa)                  /* PIC Mode */
1243                                 } /* end _PRT */
1244                         } /* end PBRa */
1245
1246                         Device(PE20) {
1247                                 Name(_ADR, 0x00150000)
1248                                 Name(_PRW, Package() {0x18, 4})
1249                                 Method(_PRT,0) {
1250                                         If(PMOD){ Return(APE0) }   /* APIC mode */
1251                                         Return (PE0)                  /* PIC Mode */
1252                                 } /* end _PRT */
1253                         } /* end PE20 */
1254                         Device(PE21) {
1255                                 Name(_ADR, 0x00150001)
1256                                 Name(_PRW, Package() {0x18, 4})
1257                                 Method(_PRT,0) {
1258                                         If(PMOD){ Return(APE1) }   /* APIC mode */
1259                                         Return (PE1)                  /* PIC Mode */
1260                                 } /* end _PRT */
1261                         } /* end PE21 */
1262                         Device(PE22) {
1263                                 Name(_ADR, 0x00150002)
1264                                 Name(_PRW, Package() {0x18, 4})
1265                                 Method(_PRT,0) {
1266                                         If(PMOD){ Return(APE2) }   /* APIC mode */
1267                                         Return (APE2)                  /* PIC Mode */
1268                                 } /* end _PRT */
1269                         } /* end PE22 */
1270                         Device(PE23) {
1271                                 Name(_ADR, 0x00150003)
1272                                 Name(_PRW, Package() {0x18, 4})
1273                                 Method(_PRT,0) {
1274                                         If(PMOD){ Return(APE3) }   /* APIC mode */
1275                                         Return (PE3)                  /* PIC Mode */
1276                                 } /* end _PRT */
1277                         } /* end PE23 */
1278
1279                         /* PCI slot 1, 2, 3 */
1280                         Device(PIBR) {
1281                                 Name(_ADR, 0x00140004)
1282                                 Name(_PRW, Package() {0x18, 4})
1283
1284                                 Method(_PRT, 0) {
1285                                         Return (PCIB)
1286                                 }
1287                         }
1288
1289                         /* Describe the Southbridge devices */
1290                         Device(STCR) {
1291                                 Name(_ADR, 0x00110000)
1292                                 #include "acpi/sata.asl"
1293                         } /* end STCR */
1294
1295                         Device(UOH1) {
1296                                 Name(_ADR, 0x00120000)
1297                                 Name(_PRW, Package() {0x0B, 3})
1298                         } /* end UOH1 */
1299
1300                         Device(UOH2) {
1301                                 Name(_ADR, 0x00120002)
1302                                 Name(_PRW, Package() {0x0B, 3})
1303                         } /* end UOH2 */
1304
1305                         Device(UOH3) {
1306                                 Name(_ADR, 0x00130000)
1307                                 Name(_PRW, Package() {0x0B, 3})
1308                         } /* end UOH3 */
1309
1310                         Device(UOH4) {
1311                                 Name(_ADR, 0x00130002)
1312                                 Name(_PRW, Package() {0x0B, 3})
1313                         } /* end UOH4 */
1314
1315                         Device(UOH5) {
1316                                 Name(_ADR, 0x00160000)
1317                                 Name(_PRW, Package() {0x0B, 3})
1318                         } /* end UOH5 */
1319
1320                         Device(UOH6) {
1321                                 Name(_ADR, 0x00160002)
1322                                 Name(_PRW, Package() {0x0B, 3})
1323                         } /* end UOH5 */
1324
1325                         Device(UEH1) {
1326                                 Name(_ADR, 0x00140005)
1327                                 Name(_PRW, Package() {0x0B, 3})
1328                         } /* end UEH1 */
1329
1330                         Device(SBUS) {
1331                                 Name(_ADR, 0x00140000)
1332                         } /* end SBUS */
1333
1334                         /* Primary (and only) IDE channel */
1335                         Device(IDEC) {
1336                                 Name(_ADR, 0x00140001)
1337                                 #include "acpi/ide.asl"
1338                         } /* end IDEC */
1339
1340                         Device(AZHD) {
1341                                 Name(_ADR, 0x00140002)
1342                                 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1343                                         Field(AZPD, AnyAcc, NoLock, Preserve) {
1344                                         offset (0x42),
1345                                         NSDI, 1,
1346                                         NSDO, 1,
1347                                         NSEN, 1,
1348                                         offset (0x44),
1349                                         IPCR, 4,
1350                                         offset (0x54),
1351                                         PWST, 2,
1352                                         , 6,
1353                                         PMEB, 1,
1354                                         , 6,
1355                                         PMST, 1,
1356                                         offset (0x62),
1357                                         MMCR, 1,
1358                                         offset (0x64),
1359                                         MMLA, 32,
1360                                         offset (0x68),
1361                                         MMHA, 32,
1362                                         offset (0x6C),
1363                                         MMDT, 16,
1364                                 }
1365
1366                                 Method(_INI) {
1367                                         If(LEqual(OSTP,3)){   /* If we are running Linux */
1368                                                 Store(zero, NSEN)
1369                                                 Store(one, NSDO)
1370                                                 Store(one, NSDI)
1371                                         }
1372                                 }
1373                         } /* end AZHD */
1374
1375                         Device(LIBR) {
1376                                 Name(_ADR, 0x00140003)
1377                                 /* Method(_INI) {
1378                                 *       DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1379                                 } */ /* End Method(_SB.SBRDG._INI) */
1380
1381                                 /* Real Time Clock Device */
1382                                 Device(RTC0) {
1383                                         Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
1384                                         Name(_CRS, ResourceTemplate() {
1385                                                 IRQNoFlags(){8}
1386                                                 IO(Decode16,0x0070, 0x0070, 0, 2)
1387                                                 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1388                                         })
1389                                 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1390
1391                                 Device(TMR) {   /* Timer */
1392                                         Name(_HID,EISAID("PNP0100"))    /* System Timer */
1393                                         Name(_CRS, ResourceTemplate() {
1394                                                 IRQNoFlags(){0}
1395                                                 IO(Decode16, 0x0040, 0x0040, 0, 4)
1396                                                 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1397                                         })
1398                                 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1399
1400                                 Device(SPKR) {  /* Speaker */
1401                                         Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
1402                                         Name(_CRS, ResourceTemplate() {
1403                                                 IO(Decode16, 0x0061, 0x0061, 0, 1)
1404                                         })
1405                                 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1406
1407                                 Device(PIC) {
1408                                         Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
1409                                         Name(_CRS, ResourceTemplate() {
1410                                                 IRQNoFlags(){2}
1411                                                 IO(Decode16,0x0020, 0x0020, 0, 2)
1412                                                 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1413                                                 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1414                                                 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1415                                         })
1416                                 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1417
1418                                 Device(MAD) { /* 8257 DMA */
1419                                         Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
1420                                         Name(_CRS, ResourceTemplate() {
1421                                                 DMA(Compatibility,BusMaster,Transfer8){4}
1422                                                 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1423                                                 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1424                                                 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1425                                                 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1426                                                 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1427                                                 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1428                                         }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1429                                 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1430
1431                                 Device(COPR) {
1432                                         Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
1433                                         Name(_CRS, ResourceTemplate() {
1434                                                 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1435                                                 IRQNoFlags(){13}
1436                                         })
1437                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1438 #if 0
1439                                 Device(HPTM) {
1440                                         Name(_HID,EISAID("PNP0103"))
1441                                         Name(CRS,ResourceTemplate()     {
1442                                                 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)     /* 1kb reserved space */
1443                                         })
1444                                         Method(_STA, 0) {
1445                                                 Return(0x0F) /* sata is visible */
1446                                         }
1447                                         Method(_CRS, 0) {
1448                                                 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1449                                                 Store(HPBA, HPBA)
1450                                                 Return(CRS)
1451                                         }
1452                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1453 #endif
1454                         } /* end LIBR */
1455
1456                         Device(HPBR) {
1457                                 Name(_ADR, 0x00140004)
1458                         } /* end HostPciBr */
1459
1460                         Device(ACAD) {
1461                                 Name(_ADR, 0x00140005)
1462                         } /* end Ac97audio */
1463
1464                         Device(ACMD) {
1465                                 Name(_ADR, 0x00140006)
1466                         } /* end Ac97modem */
1467
1468                         Name(CRES, ResourceTemplate() {
1469                                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1470
1471                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1472                                         0x0000,                 /* address granularity */
1473                                         0x0000,                 /* range minimum */
1474                                         0x0CF7,                 /* range maximum */
1475                                         0x0000,                 /* translation */
1476                                         0x0CF8                  /* length */
1477                                 )
1478
1479                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1480                                         0x0000,                 /* address granularity */
1481                                         0x0D00,                 /* range minimum */
1482                                         0xFFFF,                 /* range maximum */
1483                                         0x0000,                 /* translation */
1484                                         0xF300                  /* length */
1485                                 )
1486
1487                                 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)   /* VGA memory space */
1488 #if 0
1489                                 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)   /* Assume C0000-E0000 empty */
1490                                 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
1491
1492                                 /* DRAM Memory from 1MB to TopMem */
1493                                 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)   /* 1MB to TopMem */
1494
1495                                 /* BIOS space just below 4GB */
1496                                 DWORDMemory(
1497                                         ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1498                                         0x00,                   /* Granularity */
1499                                         0x00000000,             /* Min */
1500                                         0x00000000,             /* Max */
1501                                         0x00000000,             /* Translation */
1502                                         0x00000001,             /* Max-Min, RLEN */
1503                                         ,,
1504                                         PCBM
1505                                 )
1506
1507                                 /* DRAM memory from 4GB to TopMem2 */
1508                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1509                                         0x00000000,             /* Granularity */
1510                                         0x00000000,             /* Min */
1511                                         0x00000000,             /* Max */
1512                                         0x00000000,             /* Translation */
1513                                         0x00000001,             /* Max-Min, RLEN */
1514                                         ,,
1515                                         DMHI
1516                                 )
1517
1518                                 /* BIOS space just below 16EB */
1519                                 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1520                                         0x00000000,             /* Granularity */
1521                                         0x00000000,             /* Min */
1522                                         0x00000000,             /* Max */
1523                                         0x00000000,             /* Translation */
1524                                         0x00000001,             /* Max-Min, RLEN */
1525                                         ,,
1526                                         PEBM
1527                                 )
1528 #endif
1529                                 /* memory space for PCI BARs below 4GB */
1530                                 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1531                         }) /* End Name(_SB.PCI0.CRES) */
1532
1533                         Method(_CRS, 0) {
1534                                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1535 #if 0
1536                                 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1537                                 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1538                                 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1539                                 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1540                                 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1541                                 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1542
1543                                 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1544                                 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1545                                 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1546                                 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1547
1548                                 If(LGreater(LOMH, 0xC0000)){
1549                                         Store(0xC0000, EM1B)    /* Hole above C0000 and below E0000 */
1550                                         Subtract(LOMH, 0xC0000, EM1L)   /* subtract start, assumes allocation from C0000 going up */
1551                                 }
1552
1553                                 /* Set size of memory from 1MB to TopMem */
1554                                 Subtract(TOM1, 0x100000, DMLL)
1555
1556                                 /*
1557                                 * If(LNotEqual(TOM2, 0x00000000)){
1558                                 *       Store(0x100000000,DMHB)                 DRAM from 4GB to TopMem2
1559                                 *       Subtract(TOM2, 0x100000000, DMHL)
1560                                 * }
1561                                 */
1562
1563                                 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1564                                 If(LEqual(TOM2, 0x00000000)){
1565                                         Store(PBAD,PBMB)                        /* Reserve the "BIOS" space */
1566                                         Store(PBLN,PBML)
1567                                 }
1568                                 Else {  /* Otherwise, put the BIOS just below 16EB */
1569                                         ShiftLeft(PBAD,16,EBMB)         /* Reserve the "BIOS" space */
1570                                         Store(PBLN,EBML)
1571                                 }
1572 #endif
1573                                 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1574                                 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1575                                 /*
1576                                  * Declare memory between TOM1 and 4GB as available
1577                                  * for PCI MMIO.
1578                                  * Use ShiftLeft to avoid 64bit constant (for XP).
1579                                  * This will work even if the OS does 32bit arithmetic, as
1580                                  * 32bit (0x00000000 - TOM1) will wrap and give the same
1581                                  * result as 64bit (0x100000000 - TOM1).
1582                                  */
1583                                 Store(TOM1, MM1B)
1584                                 ShiftLeft(0x10000000, 4, Local0)
1585                                 Subtract(Local0, TOM1, Local0)
1586                                 Store(Local0, MM1L)
1587
1588                                 Return(CRES) /* note to change the Name buffer */
1589                         } /* end of Method(_SB.PCI0._CRS) */
1590
1591                         /*
1592                         *
1593                         *               FIRST METHOD CALLED UPON BOOT
1594                         *
1595                         *  1. If debugging, print current OS and ACPI interpreter.
1596                         *  2. Get PCI Interrupt routing from ACPI VSM, this
1597                         *     value is based on user choice in BIOS setup.
1598                         */
1599                         Method(_INI, 0) {
1600                                 /* DBGO("\\_SB\\_INI\n") */
1601                                 /* DBGO("   DSDT.ASL code from ") */
1602                                 /* DBGO(__DATE__) */
1603                                 /* DBGO(" ") */
1604                                 /* DBGO(__TIME__) */
1605                                 /* DBGO("\n   Sleep states supported: ") */
1606                                 /* DBGO("\n") */
1607                                 /* DBGO("   \\_OS=") */
1608                                 /* DBGO(\_OS) */
1609                                 /* DBGO("\n   \\_REV=") */
1610                                 /* DBGO(\_REV) */
1611                                 /* DBGO("\n") */
1612
1613                                 /* Determine the OS we're running on */
1614                                 CkOT()
1615
1616                                 /* On older chips, clear PciExpWakeDisEn */
1617                                 /*if (LLessEqual(\SBRI, 0x13)) {
1618                                 *       Store(0,\PWDE)
1619                                 * }
1620                                 */
1621                         } /* End Method(_SB._INI) */
1622                 } /* End Device(PCI0)  */
1623
1624                 Device(PWRB) {  /* Start Power button device */
1625                         Name(_HID, EISAID("PNP0C0C"))
1626                         Name(_UID, 0xAA)
1627                         Name(_PRW, Package () {3, 0x04})        /* wake from S1-S4 */
1628                         Name(_STA, 0x0B) /* sata is invisible */
1629                 }
1630         } /* End \_SB scope */
1631
1632         Scope(\_SI) {
1633                 Method(_SST, 1) {
1634                         /* DBGO("\\_SI\\_SST\n") */
1635                         /* DBGO("   New Indicator state: ") */
1636                         /* DBGO(Arg0) */
1637                         /* DBGO("\n") */
1638                 }
1639         } /* End Scope SI */
1640 #if 0
1641         /* SMBUS Support */
1642         Mutex (SBX0, 0x00)
1643         OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1644                 Field (SMB0, ByteAcc, NoLock, Preserve) {
1645                         HSTS,   8, /* SMBUS status */
1646                         SSTS,   8,  /* SMBUS slave status */
1647                         HCNT,   8,  /* SMBUS control */
1648                         HCMD,   8,  /* SMBUS host cmd */
1649                         HADD,   8,  /* SMBUS address */
1650                         DAT0,   8,  /* SMBUS data0 */
1651                         DAT1,   8,  /* SMBUS data1 */
1652                         BLKD,   8,  /* SMBUS block data */
1653                         SCNT,   8,  /* SMBUS slave control */
1654                         SCMD,   8,  /* SMBUS shaow cmd */
1655                         SEVT,   8,  /* SMBUS slave event */
1656                         SDAT,   8  /* SMBUS slave data */
1657         }
1658
1659         Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1660                 Store (0x1E, HSTS)
1661                 Store (0xFA, Local0)
1662                 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1663                         Stall (0x64)
1664                         Decrement (Local0)
1665                 }
1666
1667                 Return (Local0)
1668         }
1669
1670         Method (SWTC, 1, NotSerialized) {
1671                 Store (Arg0, Local0)
1672                 Store (0x07, Local2)
1673                 Store (One, Local1)
1674                 While (LEqual (Local1, One)) {
1675                         Store (And (HSTS, 0x1E), Local3)
1676                         If (LNotEqual (Local3, Zero)) { /* read sucess */
1677                                 If (LEqual (Local3, 0x02)) {
1678                                         Store (Zero, Local2)
1679                                 }
1680
1681                                 Store (Zero, Local1)
1682                         }
1683                         Else {
1684                                 If (LLess (Local0, 0x0A)) { /* read failure */
1685                                         Store (0x10, Local2)
1686                                         Store (Zero, Local1)
1687                                 }
1688                                 Else {
1689                                         Sleep (0x0A) /* 10 ms, try again */
1690                                         Subtract (Local0, 0x0A, Local0)
1691                                 }
1692                         }
1693                 }
1694
1695                 Return (Local2)
1696         }
1697
1698         Method (SMBR, 3, NotSerialized) {
1699                 Store (0x07, Local0)
1700                 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1701                         Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1702                         If (LEqual (Local0, Zero)) {
1703                                 Release (SBX0)
1704                                 Return (0x0)
1705                         }
1706
1707                         Store (0x1F, HSTS)
1708                         Store (Or (ShiftLeft (Arg1, One), One), HADD)
1709                         Store (Arg2, HCMD)
1710                         If (LEqual (Arg0, 0x07)) {
1711                                 Store (0x48, HCNT) /* read byte */
1712                         }
1713
1714                         Store (SWTC (0x03E8), Local1) /* 1000 ms */
1715                         If (LEqual (Local1, Zero)) {
1716                                 If (LEqual (Arg0, 0x07)) {
1717                                         Store (DAT0, Local0)
1718                                 }
1719                         }
1720                         Else {
1721                                 Store (Local1, Local0)
1722                         }
1723
1724                         Release (SBX0)
1725                 }
1726
1727                 /* DBGO("the value of SMBusData0 register ") */
1728                 /* DBGO(Arg2) */
1729                 /* DBGO(" is ") */
1730                 /* DBGO(Local0) */
1731                 /* DBGO("\n") */
1732
1733                 Return (Local0)
1734         }
1735
1736         /* THERMAL */
1737         Scope(\_TZ) {
1738                 Name (KELV, 2732)
1739                 Name (THOT, 800)
1740                 Name (TCRT, 850)
1741
1742                 ThermalZone(TZ00) {
1743                         Method(_AC0,0) {        /* Active Cooling 0 (0=highest fan speed) */
1744                                 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1745                                 Return(Add(0, 2730))
1746                         }
1747                         Method(_AL0,0) {        /* Returns package of cooling device to turn on */
1748                                 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1749                                 Return(Package() {\_TZ.TZ00.FAN0})
1750                         }
1751                         Device (FAN0) {
1752                                 Name(_HID, EISAID("PNP0C0B"))
1753                                 Name(_PR0, Package() {PFN0})
1754                         }
1755
1756                         PowerResource(PFN0,0,0) {
1757                                 Method(_STA) {
1758                                         Store(0xF,Local0)
1759                                         Return(Local0)
1760                                 }
1761                                 Method(_ON) {
1762                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1763                                 }
1764                                 Method(_OFF) {
1765                                         /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1766                                 }
1767                         }
1768
1769                         Method(_HOT,0) {        /* return hot temp in tenths degree Kelvin */
1770                                 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1771                                 Return (Add (THOT, KELV))
1772                         }
1773                         Method(_CRT,0) {        /* return critical temp in tenths degree Kelvin */
1774                                 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1775                                 Return (Add (TCRT, KELV))
1776                         }
1777                         Method(_TMP,0) {        /* return current temp of this zone */
1778                                 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1779                                 If (LGreater (Local0, 0x10)) {
1780                                         Store (Local0, Local1)
1781                                 }
1782                                 Else {
1783                                         Add (Local0, THOT, Local0)
1784                                         Return (Add (400, KELV))
1785                                 }
1786
1787                                 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1788                                 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1789                                 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1790                                 If (LGreater (Local0, 0x10)) {
1791                                         If (LGreater (Local0, Local1)) {
1792                                                 Store (Local0, Local1)
1793                                         }
1794
1795                                         Multiply (Local1, 10, Local1)
1796                                         Return (Add (Local1, KELV))
1797                                 }
1798                                 Else {
1799                                         Add (Local0, THOT, Local0)
1800                                         Return (Add (400 , KELV))
1801                                 }
1802                         } /* end of _TMP */
1803                 } /* end of TZ00 */
1804         }
1805 #endif
1806 }
1807 /* End of ASL file */