2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 * AMD User options selection for a Brazos platform solution system
25 * This file is placed in the user's platform directory and contains the
26 * build option selections desired for that platform.
28 * For Information about this file, see @ref platforminstall.
30 * @xrefitem bom "File Content Label" "Release Content"
32 * @e sub-project: Core
33 * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
37 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
40 /* Select the cpu family. */
41 #define INSTALL_FAMILY_10_SUPPORT FALSE
42 #define INSTALL_FAMILY_12_SUPPORT FALSE
43 #define INSTALL_FAMILY_14_SUPPORT TRUE
44 #define INSTALL_FAMILY_15_SUPPORT FALSE
46 /* Select the cpu socket type. */
47 #define INSTALL_G34_SOCKET_SUPPORT FALSE
48 #define INSTALL_C32_SOCKET_SUPPORT FALSE
49 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
50 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
51 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
52 #define INSTALL_FS1_SOCKET_SUPPORT FALSE
53 #define INSTALL_FM1_SOCKET_SUPPORT FALSE
54 #define INSTALL_FP1_SOCKET_SUPPORT FALSE
55 #define INSTALL_FT1_SOCKET_SUPPORT TRUE
56 #define INSTALL_AM3_SOCKET_SUPPORT FALSE
59 * Agesa optional capabilities selection.
60 * Uncomment and mark FALSE those features you wish to include in the build.
61 * Comment out or mark TRUE those features you want to REMOVE from the build.
64 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
65 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
66 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
67 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
69 #define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
70 #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
71 #define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
72 #define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
73 #define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
74 #define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
75 #define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
76 #define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
77 #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
78 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
80 #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
81 #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
82 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
83 #define BLDOPT_REMOVE_ECC_SUPPORT FALSE
84 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
85 #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
86 #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
87 #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
88 #define BLDOPT_REMOVE_DQS_TRAINING FALSE
89 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
90 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
91 #define BLDOPT_REMOVE_ACPI_PSTATES FALSE
92 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
93 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
94 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
95 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
96 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
97 #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
98 #define BLDOPT_REMOVE_SRAT TRUE
99 #define BLDOPT_REMOVE_SLIT TRUE
100 #define BLDOPT_REMOVE_WHEA TRUE
101 #define BLDOPT_REMOVE_DMI TRUE
102 #define BLDOPT_REMOVE_HT_ASSIST TRUE
103 #define BLDOPT_REMOVE_ATM_MODE TRUE
104 //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
105 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
106 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
107 //#define BLDOPT_REMOVE_C6_STATE TRUE
108 #define BLDOPT_REMOVE_GFX_RECOVERY TRUE
109 #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
112 * Agesa entry points used in this implementation.
114 #define AGESA_ENTRY_INIT_RESET TRUE
115 #define AGESA_ENTRY_INIT_RECOVERY FALSE
116 #define AGESA_ENTRY_INIT_EARLY TRUE
117 #define AGESA_ENTRY_INIT_POST TRUE
118 #define AGESA_ENTRY_INIT_ENV TRUE
119 #define AGESA_ENTRY_INIT_MID TRUE
120 #define AGESA_ENTRY_INIT_LATE TRUE
121 #define AGESA_ENTRY_INIT_S3SAVE TRUE
122 #define AGESA_ENTRY_INIT_RESUME TRUE
123 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
124 #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
126 #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
127 #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
129 #define BLDCFG_VRM_CURRENT_LIMIT 24000
130 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
131 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
132 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
133 #define BLDCFG_VRM_SLEW_RATE 5000
134 //#define BLDCFG_VRM_NB_SLEW_RATE 5000
135 //#define BLDCFG_VRM_ADDITIONAL_DELAY 0
136 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
137 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
138 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
139 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
140 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
142 //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
143 //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
144 //#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
145 #define BLDCFG_PLAT_NUM_IO_APICS 3
146 //#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
147 //#define BLDCFG_PLATFORM_C1E_OPDATA 0
148 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
149 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
150 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
151 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
152 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
153 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
154 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
155 #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
156 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
157 //#define BLDCFG_STARTING_BUSNUM 0
158 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8
159 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20
160 //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
161 //#define BLDCFG_BUID_SWAP_LIST 0
162 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
163 //#define BLDCFG_HTFABRIC_LIMITS_LIST 0
164 //#define BLDCFG_HTCHAIN_LIMITS_LIST 0
165 //#define BLDCFG_BUS_NUMBERS_LIST 0
166 //#define BLDCFG_IGNORE_LINK_LIST 0
167 //#define BLDCFG_LINK_SKIP_REGANG_LIST 0
168 //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
169 //#define BLDCFG_USE_HT_ASSIST TRUE
170 //#define BLDCFG_USE_ATM_MODE TRUE
171 //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
172 #define BLDCFG_S3_LATE_RESTORE FALSE
173 //#define BLDCFG_USE_32_BYTE_REFRESH FALSE
174 //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
175 //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
176 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
177 //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
178 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
179 #define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE
180 //#define BLDCFG_CFG_ABM_SUPPORT FALSE
181 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
182 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
183 //#define BLDCFG_MEM_INIT_PSTATE 0
184 //#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
185 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
186 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
187 //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
188 //#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
189 #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
190 #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
191 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
192 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
193 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
194 #define BLDCFG_MEMORY_POWER_DOWN TRUE
195 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
196 //#define BLDCFG_ONLINE_SPARE FALSE
197 //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
198 #define BLDCFG_BANK_SWIZZLE TRUE
199 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
200 #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
201 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
202 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
203 #define BLDCFG_USE_BURST_MODE FALSE
204 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
205 //#define BLDCFG_ENABLE_ECC_FEATURE TRUE
206 //#define BLDCFG_ECC_REDIRECTION FALSE
207 //#define BLDCFG_SCRUB_DRAM_RATE 0
208 //#define BLDCFG_SCRUB_L2_RATE 0
209 //#define BLDCFG_SCRUB_L3_RATE 0
210 //#define BLDCFG_SCRUB_IC_RATE 0
211 //#define BLDCFG_SCRUB_DC_RATE 0
212 //#define BLDCFG_ECC_SYNC_FLOOD 0
213 //#define BLDCFG_ECC_SYMBOL_SIZE 0
214 //#define BLDCFG_1GB_ALIGN FALSE
215 #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
216 #define BLDCFG_UMA_ALLOCATION_SIZE 0
217 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
218 #define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
219 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
220 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
223 * Agesa configuration values selection.
224 * Uncomment and specify the value for the configuration options
225 * needed by the system.
228 #include "CommonReturns.h"
230 /* The fixed MTRR values to be set after memory initialization. */
231 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
233 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
234 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
235 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
236 { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
237 { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
238 { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
239 { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
240 { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
241 { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
242 { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
243 { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
244 { CPU_LIST_TERMINAL }
247 /* Include the files that instantiate the configuration definitions. */
249 #include "cpuRegisters.h"
250 #include "cpuFamRegisters.h"
251 #include "cpuFamilyTranslation.h"
252 #include "AdvancedApi.h"
253 #include "heapManager.h"
254 #include "CreateStruct.h"
255 #include "cpuFeatures.h"
257 #include "cpuEarlyInit.h"
258 #include "cpuLateInit.h"
259 #include "GnbInterface.h"
261 /*****************************************************************************
262 * Define the RELEASE VERSION string
264 * The Release Version string should identify the next planned release.
265 * When a branch is made in preparation for a release, the release manager
266 * should change/confirm that the branch version of this file contains the
267 * string matching the desired version for the release. The trunk version of
268 * the file should always contain a trailing 'X'. This will make sure that a
269 * development build from trunk will not be confused for a released version.
270 * The release manager will need to remove the trailing 'X' and update the
271 * version string as appropriate for the release. The trunk copy of this file
272 * should also be updated/incremented for the next expected version, + trailing 'X'
273 ****************************************************************************/
274 // This is the delivery package title, "BrazosPI"
275 // This string MUST be exactly 8 characters long
276 #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
278 // This is the release version number of the AGESA component
279 // This string MUST be exactly 12 characters long
280 #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
282 /* MEMORY_BUS_SPEED */
283 #define DDR400_FREQUENCY 200 ///< DDR 400
284 #define DDR533_FREQUENCY 266 ///< DDR 533
285 #define DDR667_FREQUENCY 333 ///< DDR 667
286 #define DDR800_FREQUENCY 400 ///< DDR 800
287 #define DDR1066_FREQUENCY 533 ///< DDR 1066
288 #define DDR1333_FREQUENCY 667 ///< DDR 1333
289 #define DDR1600_FREQUENCY 800 ///< DDR 1600
290 #define DDR1866_FREQUENCY 933 ///< DDR 1866
291 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
294 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
295 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
297 /* USER_MEMORY_TIMING_MODE */
298 #define TIMING_MODE_AUTO 0 ///< Use best rate possible
299 #define TIMING_MODE_LIMITED 1 ///< Set user top limit
300 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
302 /* POWER_DOWN_MODE */
303 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
304 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
306 // The following definitions specify the default values for various parameters in which there are
307 // no clearly defined defaults to be used in the common file. The values below are based on product
308 // and BKDG content, please consult the AGESA Memory team for consultation.
309 #define DFLT_SCRUB_DRAM_RATE (0)
310 #define DFLT_SCRUB_L2_RATE (0)
311 #define DFLT_SCRUB_L3_RATE (0)
312 #define DFLT_SCRUB_IC_RATE (0)
313 #define DFLT_SCRUB_DC_RATE (0)
314 #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
315 #define DFLT_VRM_SLEW_RATE (5000)
317 // Instantiate all solution relevant data.
318 #include "PlatformInstall.h"
320 /*----------------------------------------------------------------------------------------
321 * CUSTOMER OVERIDES MEMORY TABLE
322 *----------------------------------------------------------------------------------------
326 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
327 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
328 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
329 * use its default conservative settings.
331 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
333 // The following macros are supported (use comma to separate macros):
335 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
336 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
337 // AGESA will base on this value to disable unused MemClk to save power.
339 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
340 // Bit AM3/S1g3 pin name
341 // 0 M[B,A]_CLK_H/L[0]
342 // 1 M[B,A]_CLK_H/L[1]
343 // 2 M[B,A]_CLK_H/L[2]
344 // 3 M[B,A]_CLK_H/L[3]
345 // 4 M[B,A]_CLK_H/L[4]
346 // 5 M[B,A]_CLK_H/L[5]
347 // 6 M[B,A]_CLK_H/L[6]
348 // 7 M[B,A]_CLK_H/L[7]
349 // And platform has the following routing:
350 // CS0 M[B,A]_CLK_H/L[4]
351 // CS1 M[B,A]_CLK_H/L[2]
352 // CS2 M[B,A]_CLK_H/L[3]
353 // CS3 M[B,A]_CLK_H/L[5]
354 // Then platform can specify the following macro:
355 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
357 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
358 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
359 // AGESA will base on this value to tristate unused CKE to save power.
361 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
362 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
363 // AGESA will base on this value to tristate unused ODT pins to save power.
365 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
366 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
367 // AGESA will base on this value to tristate unused Chip select to save power.
369 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
370 // Specifies the number of DIMM slots per channel.
372 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
373 // Specifies the number of Chip selects per channel.
375 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
376 // Specifies the number of channels per socket.
378 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
379 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
381 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
382 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
384 // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
385 // Byte6Seed, Byte7Seed, ByteEccSeed)
386 // Specifies the write leveling seed for a channel of a socket.
388 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
389 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
394 * These tables are optional and may be used to adjust memory timing settings
400 CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
402 // Hardcoded Memory Training Values
404 // The following macro should be used to override training values for your platform
406 // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
409 // The following training hardcode values are example values that were taken from a tilapia motherboard
410 // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
411 // the table and replace the byte lane values with your own.
413 // ------------------ BYTE LANES ----------------------
414 // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
416 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
417 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
418 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
419 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
421 // DQS Receiver Enable
422 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
423 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
424 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
425 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
428 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
429 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
430 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
431 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
434 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
435 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
436 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
437 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
438 //--------------------------------------------------------------------------------------------------------------------------------------------------
440 NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
442 CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
444 /* ***************************************************************************
445 * Optional User code to be included into the AGESA build
446 * These may be 32-bit call-out routines...
451 // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
454 // /* platform code to read an SPD... */