src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define RAMINIT_SYSINFO 1
   5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   6
   7 #define SET_NB_CFG_54 1
   8
   9 //used by raminit
  10 #define QRANK_DIMM_SUPPORT 1
  11
  12 //used by incoherent_ht
  13 //#define K8_SCAN_PCI_BUS 1
  14 //#define K8_ALLOCATE_IO_RANGE 1
  15
  16
  17 //used by init_cpus and fidvid
  18 #define K8_SET_FIDVID 0
  19 //if we want to wait for core1 done before DQS training, set it to 0
  20 #define K8_SET_FIDVID_CORE0_ONLY 1
  21
  22 #if K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <device/pci_def.h>
  28 #include <device/pci_ids.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include "option_table.h"
  34 #include "pc80/mc146818rtc_early.c"
  35
  36
  37 #if 0
  38 static void post_code(uint8_t value) {
  39 #if 1
  40         int i;
  41         for(i=0;i<0x80000;i++) {
  42                 outb(value, 0x80);
  43         }
  44 #endif
  45 }
  46 #endif
  47 #if USE_FAILOVER_IMAGE==0
  48 #include "pc80/serial.c"
  49 #include "arch/i386/lib/console.c"
  50 #include <cpu/amd/model_fxx_rev.h>
  51 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  52 #include "northbridge/amd/amdk8/raminit.h"
  53 #include "cpu/amd/model_fxx/apic_timer.c"
  54 #endif
  55
  56
  57
  58 #include "cpu/x86/lapic/boot_cpu.c"
  59 #include "northbridge/amd/amdk8/reset_test.c"
  60
  61 #if USE_FAILOVER_IMAGE==0
  62 #include "cpu/x86/bist.h"
  63
  64 #include "lib/delay.c"
  65
  66 #if CONFIG_USE_INIT == 0
  67         #include "lib/memcpy.c"
  68 #endif
  69 #include "northbridge/amd/amdk8/debug.c"
  70 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  71 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  72
  73 #include "northbridge/amd/amdk8/setup_resource_map.c"
  74
  75 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  76
  77 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  78
  79 static void memreset_setup(void)
  80 {
  81         //GPIO on amd8111 to enable MEMRST ????
  82         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  83         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  84 }
  85
  86 static void memreset(int controllers, const struct mem_controller *ctrl)
  87 {
  88 }
  89
  90 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  91 {
  92 #define SMBUS_HUB 0x18
  93         int ret,i;
  94         unsigned device=(ctrl->channel0[0])>>8;
  95         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  96         i=2;
  97         do {
  98                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  99         } while ((ret!=0) && (i-->0));
 100
 101         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 102 }
 103 #if 0
 104 static inline void change_i2c_mux(unsigned device)
 105 {
 106 #define SMBUS_HUB 0x18
 107         int ret, i;
 108         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
 109         i=2;
 110         do {
 111                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 112                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
 113         } while ((ret!=0) && (i-->0));
 114         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
 115         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
 116 }
 117 #endif
 118
 119 static inline int spd_read_byte(unsigned device, unsigned address)
 120 {
 121         return smbus_read_byte(device, address);
 122 }
 123
 124 #include "northbridge/amd/amdk8/amdk8.h"
 125 #include "northbridge/amd/amdk8/coherent_ht.c"
 126
 127 #include "northbridge/amd/amdk8/incoherent_ht.c"
 128
 129 #include "northbridge/amd/amdk8/raminit.c"
 130
 131 #include "sdram/generic_sdram.c"
 132
 133  /* tyan does not want the default */
 134 #include "resourcemap.c"
 135
 136 #include "cpu/amd/dualcore/dualcore.c"
 137
 138 #define RC0 ((1<<0)<<8)
 139 #define RC1 ((1<<1)<<8)
 140 #define RC2 ((1<<2)<<8)
 141 #define RC3 ((1<<3)<<8)
 142
 143 #define DIMM0 0x50
 144 #define DIMM1 0x51
 145 #define DIMM2 0x52
 146 #define DIMM3 0x53
 147 #define DIMM4 0x54
 148 #define DIMM5 0x55
 149 #define DIMM6 0x56
 150 #define DIMM7 0x57
 151
 152
 153 #include "cpu/amd/car/copy_and_run.c"
 154 #include "cpu/amd/car/post_cache_as_ram.c"
 155
 156 #include "cpu/amd/model_fxx/init_cpus.c"
 157
 158 #include "cpu/amd/model_fxx/fidvid.c"
 159 #endif
 160
 161 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 162
 163 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 164 #include "northbridge/amd/amdk8/early_ht.c"
 165
 166 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 167 {
 168
 169         unsigned last_boot_normal_x = last_boot_normal();
 170
 171         /* Is this a cpu only reset? or Is this a secondary cpu? */
 172         if ((cpu_init_detectedx) || (!boot_cpu())) {
 173                 if (last_boot_normal_x) {
 174                         goto normal_image;
 175                 } else {
 176                         goto fallback_image;
 177                 }
 178         }
 179
 180         /* Nothing special needs to be done to find bus 0 */
 181         /* Allow the HT devices to be found */
 182
 183         enumerate_ht_chain();
 184
 185         /* Setup the rom access for 4M */
 186         amd8111_enable_rom();
 187
 188         /* Is this a deliberate reset by the bios */
 189         if (bios_reset_detected() && last_boot_normal_x) {
 190                 goto normal_image;
 191         }
 192         /* This is the primary cpu how should I boot? */
 193         else if (do_normal_boot()) {
 194                 goto normal_image;
 195         }
 196         else {
 197                 goto fallback_image;
 198         }
 199  normal_image:
 200         __asm__ volatile ("jmp __normal_image"
 201                 : /* outputs */
 202                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 203                 );
 204
 205  fallback_image:
 206 #if HAVE_FAILOVER_BOOT==1
 207         __asm__ volatile ("jmp __fallback_image"
 208                 : /* outputs */
 209                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 210                 )
 211 #endif
 212         ;
 213 }
 214 #endif
 215
 216 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 217
 218 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 219 {
 220 #if HAVE_FAILOVER_BOOT==1
 221     #if USE_FAILOVER_IMAGE==1
 222         failover_process(bist, cpu_init_detectedx);
 223     #else
 224         real_main(bist, cpu_init_detectedx);
 225     #endif
 226 #else
 227     #if USE_FALLBACK_IMAGE == 1
 228         failover_process(bist, cpu_init_detectedx);
 229     #endif
 230         real_main(bist, cpu_init_detectedx);
 231 #endif
 232 }
 233
 234 #if USE_FAILOVER_IMAGE==0
 235
 236 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 237 {
 238         static const uint16_t spd_addr[] = {
 239                         //first node
 240                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 241                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 242 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 243                         //second node
 244                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 245                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 246 #endif
 247 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 248                         // third node
 249                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 250                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 251                         // four node
 252                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 253                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 254 #endif
 255
 256         };
 257
 258         struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 259
 260         int needs_reset; int i;
 261         unsigned bsp_apicid = 0;
 262
 263         if (bist == 0) {
 264                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 265         }
 266
 267 //      post_code(0x32);
 268
 269         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 270         uart_init();
 271         console_init();
 272
 273 //      dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
 274
 275         /* Halt if there was a built in self test failure */
 276         report_bist_failure(bist);
 277
 278         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 279
 280         setup_mb_resource_map();
 281 #if 0
 282         dump_pci_device(PCI_DEV(0, 0x18, 0));
 283         dump_pci_device(PCI_DEV(0, 0x19, 0));
 284 #endif
 285
 286         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 287
 288 #if MEM_TRAIN_SEQ == 1
 289         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 290 #endif
 291         setup_coherent_ht_domain(); // routing table and start other core0
 292
 293         wait_all_core0_started();
 294 #if CONFIG_LOGICAL_CPUS==1
 295         // It is said that we should start core1 after all core0 launched
 296         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 297          * So here need to make sure last core0 is started, esp for two way system,
 298          * (there may be apic id conflicts in that case)
 299          */
 300         start_other_cores();
 301         wait_all_other_cores_started(bsp_apicid);
 302 #endif
 303
 304         /* it will set up chains and store link pair for optimization later */
 305         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 306
 307 #if 0
 308         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 309         needs_reset = optimize_link_coherent_ht();
 310         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 311 #endif
 312
 313 #if K8_SET_FIDVID == 1
 314
 315         {
 316                 msr_t msr;
 317                 msr=rdmsr(0xc0010042);
 318                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 319
 320         }
 321
 322         enable_fid_change();
 323
 324         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 325
 326         init_fidvid_bsp(bsp_apicid);
 327
 328         // show final fid and vid
 329         {
 330                 msr_t msr;
 331                 msr=rdmsr(0xc0010042);
 332                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 333
 334         }
 335 #endif
 336
 337 #if 1
 338         needs_reset = optimize_link_coherent_ht();
 339         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 340
 341         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 342         if (needs_reset) {
 343                 print_info("ht reset -\r\n");
 344                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 345         }
 346 #endif
 347         allow_all_aps_stop(bsp_apicid);
 348
 349         //It's the time to set ctrl in sysinfo now;
 350         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 351
 352         enable_smbus();
 353
 354 #if 0
 355         for(i=0;i<4;i++) {
 356                 activate_spd_rom(&cpu[i]);
 357                 dump_smbus_registers();
 358         }
 359 #endif
 360
 361 #if 0
 362         for(i=1;i<256;i<<=1) {
 363                 change_i2c_mux(i);
 364                 dump_smbus_registers();
 365         }
 366 #endif
 367
 368         memreset_setup();
 369
 370         //do we need apci timer, tsc...., only debug need it for better output
 371         /* all ap stopped? */
 372 //        init_timer(); // Need to use TMICT to synconize FID/VID
 373
 374         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 375
 376 #if 0
 377         print_pci_devices();
 378 #endif
 379
 380 #if 0
 381 //        dump_pci_devices();
 382         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 383         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 384 #endif
 385
 386         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 387
 388 }
 389 #endif