1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/failovercalculation.lb
8 ## Build the objects we have code for in this directory.
15 #needed by irq_tables and mptable and acpi_tables
18 if CONFIG_HAVE_MP_TABLE
22 if CONFIG_HAVE_PIRQ_TABLE
26 #if CONFIG_HAVE_ACPI_TABLES
27 # object acpi_tables.o
29 # if CONFIG_SB_HT_CHAIN_ON_BUS0
35 # if CONFIG_ACPI_SSDTX_NUM
36 # if CONFIG_SB_HT_CHAIN_ON_BUS0
44 if CONFIG_HAVE_ACPI_TABLES
48 depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
49 action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
50 action "mv dsdt_lb.hex dsdt.c"
54 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
56 if CONFIG_ACPI_SSDTX_NUM
58 depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
59 action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
60 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
61 action "mv pci2.hex ssdt2.c"
65 depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
66 action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
67 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
68 action "mv pci3.hex ssdt3.c"
72 depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
73 action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
74 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
75 action "mv pci4.hex ssdt4.c"
82 # compile cache_as_ram.c to auto.o
83 makerule ./cache_as_ram_auto.o
84 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
85 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
89 #compile cache_as_ram.c to auto.inc
90 makerule ./cache_as_ram_auto.inc
91 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
92 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
93 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
94 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
98 if CONFIG_USE_FAILOVER_IMAGE
100 if CONFIG_AP_CODE_IN_CAR
101 makerule ./apc_auto.o
102 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
103 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
105 ldscript /arch/i386/init/ldscript_apc.lb
110 ## Build our 16 bit and 32 bit coreboot entry code
113 if CONFIG_HAVE_FAILOVER_BOOT
114 if CONFIG_USE_FAILOVER_IMAGE
115 mainboardinit cpu/x86/16bit/entry16.inc
116 ldscript /cpu/x86/16bit/entry16.lds
119 if CONFIG_USE_FALLBACK_IMAGE
120 mainboardinit cpu/x86/16bit/entry16.inc
121 ldscript /cpu/x86/16bit/entry16.lds
125 mainboardinit cpu/x86/32bit/entry32.inc
127 ldscript /cpu/x86/32bit/entry32.lds
131 ldscript /cpu/amd/car/cache_as_ram.lds
135 ## Build our reset vector (This is where coreboot is entered)
137 if CONFIG_HAVE_FAILOVER_BOOT
138 if CONFIG_USE_FAILOVER_IMAGE
139 mainboardinit cpu/x86/16bit/reset16.inc
140 ldscript /cpu/x86/16bit/reset16.lds
142 mainboardinit cpu/x86/32bit/reset32.inc
143 ldscript /cpu/x86/32bit/reset32.lds
146 if CONFIG_USE_FALLBACK_IMAGE
147 mainboardinit cpu/x86/16bit/reset16.inc
148 ldscript /cpu/x86/16bit/reset16.lds
150 mainboardinit cpu/x86/32bit/reset32.inc
151 ldscript /cpu/x86/32bit/reset32.lds
156 ## Include an id string (For safe flashing)
158 mainboardinit arch/i386/lib/id.inc
159 ldscript /arch/i386/lib/id.lds
162 ## Setup Cache-As-Ram
164 mainboardinit cpu/amd/car/cache_as_ram.inc
167 ### This is the early phase of coreboot startup
168 ### Things are delicate and we test to see if we should
169 ### failover to another image.
171 if CONFIG_HAVE_FAILOVER_BOOT
172 if CONFIG_USE_FAILOVER_IMAGE
173 ldscript /arch/i386/lib/failover_failover.lds
176 if CONFIG_USE_FALLBACK_IMAGE
177 ldscript /arch/i386/lib/failover.lds
182 ### O.k. We aren't just an intermediary anymore!
189 initobject cache_as_ram_auto.o
191 mainboardinit ./cache_as_ram_auto.inc
195 ## Include the secondary Configuration files
199 # sample config for amd/serengeti_cheetah
200 chip northbridge/amd/amdk8/root_complex
201 device apic_cluster 0 on
202 chip cpu/amd/socket_F
206 device pci_domain 0 on
207 chip northbridge/amd/amdk8
208 device pci 18.0 on # northbridge
209 # devices on link 0, link 0 == LDT 0
210 chip southbridge/amd/amd8132
211 # the on/off keyword is mandatory
212 device pci 0.0 on end
213 device pci 0.1 on end
214 device pci 1.0 on end
215 device pci 1.1 on end
217 chip southbridge/amd/amd8111
218 # this "device pci 0.0" is the parent the next one
221 device pci 0.0 on end
222 device pci 0.1 on end
223 device pci 0.2 off end
224 device pci 1.0 off end
227 chip superio/winbond/w83627hf
228 device pnp 2e.0 off # Floppy
233 device pnp 2e.1 off # Parallel Port
237 device pnp 2e.2 on # Com1
241 device pnp 2e.3 off # Com2
245 device pnp 2e.5 on # Keyboard
251 device pnp 2e.6 off # CIR
254 device pnp 2e.7 off # GAME_MIDI_GIPO1
259 device pnp 2e.8 off end # GPIO2
260 device pnp 2e.9 off end # GPIO3
261 device pnp 2e.a off end # ACPI
262 device pnp 2e.b on # HW Monitor
268 device pci 1.1 on end
269 device pci 1.2 on end
271 chip drivers/i2c/i2cmux # pca9556 smbus mux
272 device i2c 18 on #0 pca9516 1
273 chip drivers/generic/generic #dimm 0-0-0
276 chip drivers/generic/generic #dimm 0-0-1
279 chip drivers/generic/generic #dimm 0-1-0
282 chip drivers/generic/generic #dimm 0-1-1
286 device i2c 18 on #1 pca9516 2
287 chip drivers/generic/generic #dimm 1-0-0
290 chip drivers/generic/generic #dimm 1-0-1
293 chip drivers/generic/generic #dimm 1-1-0
296 chip drivers/generic/generic #dimm 1-1-1
299 chip drivers/generic/generic #dimm 1-2-0
302 chip drivers/generic/generic #dimm 1-2-1
305 chip drivers/generic/generic #dimm 1-3-0
308 chip drivers/generic/generic #dimm 1-3-1
314 device pci 1.5 off end
315 device pci 1.6 off end
316 register "ide0_enable" = "1"
317 register "ide1_enable" = "1"
319 end # device pci 18.0
321 device pci 18.0 on end
322 device pci 18.0 on end
323 device pci 18.1 on end
324 device pci 18.2 on end
325 device pci 18.3 on end
327 chip northbridge/amd/amdk8
328 device pci 19.0 on # northbridge
329 chip southbridge/amd/amd8151
330 # the on/off keyword is mandatory
331 device pci 0.0 on end
332 device pci 1.0 on end
334 end # device pci 19.0
336 device pci 19.0 on end
337 device pci 19.0 on end
338 device pci 19.1 on end
339 device pci 19.2 on end
340 device pci 19.3 on end
345 # chip drivers/generic/debug
346 # device pnp 0.0 off end # chip name
347 # device pnp 0.1 on end # pci_regs_all
348 # device pnp 0.2 off end # mem
349 # device pnp 0.3 off end # cpuid
350 # device pnp 0.4 off end # smbus_regs_all
351 # device pnp 0.5 off end # dual core msr
352 # device pnp 0.6 off end # cache size
353 # device pnp 0.7 off end # tsc