2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <device/pci.h>
26 #include <cpu/amd/amdfam10_sysconf.h>
28 extern u8 bus_rs780[11];
29 extern u8 bus_sb700[2];
31 extern u32 apicid_sb700;
33 extern u32 sbdn_rs780;
34 extern u32 sbdn_sb700;
36 static void *smp_write_config_table(void *v)
38 struct mp_config_table *mc;
41 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
43 mptable_init(mc, LAPIC_ADDR);
45 smp_write_processors(mc);
49 mptable_write_buses(mc, NULL, &bus_isa);
51 /* I/O APICs: APIC ID Version State Address */
58 dev_find_slot(bus_sb700[0],
59 PCI_DEVFN(sbdn_sb700 + 0x14, 0));
61 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
62 smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
64 /* Initialize interrupt mapping */
66 byte = pci_read_config8(dev, 0x63);
68 byte |= 0; /* 0: INTA, ...., 7: INTH */
69 pci_write_config8(dev, 0x63, byte);
72 dword = pci_read_config32(dev, 0xac);
74 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
75 /* dword |= 1<<22; PIC and APIC co exists */
76 pci_write_config32(dev, 0xac, dword);
79 * 00:12.0: PROG SATA : INT F
87 * 00:14.2: Prog HDA : INT E
94 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
95 #define IO_LOCAL_INT(type, intr, apicid, pin) \
96 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
98 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
100 /* PCI interrupts are level triggered, and are
101 * associated with a specific bus/device/function tuple.
103 #if CONFIG_GENERATE_ACPI_TABLES == 0
104 #define PCI_INT(bus, dev, fn, pin) \
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
107 #define PCI_INT(bus, dev, fn, pin)
110 /* changes added to match acpi tables */
111 PCI_INT(0x0, 0x02, 0x0, 0x12);
112 PCI_INT(0x0, 0x03, 0x0, 0x13);
113 PCI_INT(0x0, 0x04, 0x0, 0x10);
114 PCI_INT(0x0, 0x09, 0x0, 0x11);
115 PCI_INT(0x0, 0x0A, 0x0, 0x12);
116 PCI_INT(0x0, 0x12, 0x2, 0x12);
117 PCI_INT(0x0, 0x12, 0x3, 0x13);
118 PCI_INT(0x0, 0x13, 0x2, 0x10);
119 PCI_INT(0x0, 0x13, 0x2, 0x11);
120 PCI_INT(0x0, 0x14, 0x1, 0x11);
121 PCI_INT(0x0, 0x14, 0x3, 0x13);
122 PCI_INT(0x1, 0x05, 0x2, 0x10);
123 PCI_INT(0x1, 0x05, 0x3, 0x11);
124 PCI_INT(0x2, 0x00, 0x0, 0x12);
125 PCI_INT(0x2, 0x00, 0x1, 0x13);
126 PCI_INT(0x2, 0x00, 0x2, 0x10);
127 PCI_INT(0x2, 0x00, 0x3, 0x11);
129 /* RS780 PCI to PCI bridge (PCIE port 4) */
130 PCI_INT(0x0, 0x09, 0x0, 0x11);
133 PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
134 PCI_INT(0x0, 0x12, 0x1, 0x11);
135 PCI_INT(0x0, 0x13, 0x0, 0x12);
136 PCI_INT(0x0, 0x13, 0x1, 0x13);
137 PCI_INT(0x0, 0x14, 0x0, 0x10);
140 PCI_INT(0x0, 0x11, 0x0, 0x16);
142 /* HD Audio: b0:d20:f1:reg63 should be 0. */
143 PCI_INT(0x0, 0x14, 0x2, 0x12);
145 /* on board NIC & Slot PCIE. */
146 /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
147 /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
148 PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */
149 PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */
150 /* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); *//* Dev 2, external GFX */
151 /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
152 /* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */
153 /* configuration B doesnt need dev 5,6,7 */
155 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
156 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
157 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
159 /* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */
160 PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */
161 /* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */
165 PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
166 PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
167 PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
168 PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
171 PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
172 PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
173 PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
174 PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
177 PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
178 PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
179 PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
180 PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
182 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
183 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
184 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
185 /* There is no extension information... */
187 /* Compute the checksums */
188 return mptable_finalize(mc);
191 unsigned long write_smp_table(unsigned long addr)
194 v = smp_write_floating_table(addr, 0);
195 return (unsigned long)smp_write_config_table(v);