src/drivers/ati/ragexl/xlinit.c

   1 /*
   2  *  ATI Rage XL Initialization. Support for Xpert98 and Victoria
   3  *  PCI cards.
   4  *
   5  *  Copyright (C) 2002 MontaVista Software Inc.
   6  *  Author: MontaVista Software, Inc.
   7  *              stevel@mvista.com or source@mvista.com
   8  *  Copyright (C) 2004 Tyan Computer.
   9  *  Auther: Yinghai Lu   yhlu@tyan.com
  10  *         move to coreboot
  11  * This code is distributed without warranty under the GPL v2 (see COPYING) *
  12  */
  13 #include <delay.h>
  14 #include <stdlib.h>
  15 #include <string.h>
  16 #include <arch/io.h>
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ops.h>
  23
  24 #if CONFIG_CONSOLE_BTEXT==1
  25
  26 #define PLL_CRTC_DECODE 0
  27 #define SUPPORT_8_BPP_ABOVE 0
  28
  29 #include "fb.h"
  30 #include "fbcon.h"
  31
  32 struct aty_cmap_regs {
  33         u8 windex;
  34         u8 lut;
  35         u8 mask;
  36         u8 rindex;
  37         u8 cntl;
  38 };
  39
  40 #include <console/btext.h>
  41
  42 #endif /*CONFIG_CONSOLE_BTEXT*/
  43
  44 #include "mach64.h"
  45
  46 #include "atyfb.h"
  47
  48 #include "mach64_ct.c"
  49
  50 #define MPLL_GAIN       0xad
  51 #define VPLL_GAIN       0xd5
  52
  53 #define HAS_VICTORIA 0
  54
  55 enum {
  56 #if HAS_VICTORIA==1
  57         VICTORIA = 0,
  58         XPERT98,
  59 #else
  60         XPERT98=0,
  61 #endif
  62         NUM_XL_CARDS
  63 };
  64
  65 //static struct aty_pll_ops aty_pll_ct;
  66
  67 #define DEFAULT_CARD XPERT98
  68 static int xl_card = DEFAULT_CARD;
  69
  70 static const struct xl_card_cfg_t {
  71         int ref_crystal; // 10^4 Hz
  72         int mem_type;
  73         int mem_size;
  74         u32 mem_cntl;
  75         u32 ext_mem_cntl;
  76         u32 mem_addr_config;
  77         u32 bus_cntl;
  78         u32 dac_cntl;
  79         u32 hw_debug;
  80         u32 custom_macro_cntl;
  81         u8  dll2_cntl;
  82         u8  pll_yclk_cntl;
  83 } card_cfg[NUM_XL_CARDS] = {
  84 #if HAS_VICTORIA==1
  85         // VICTORIA
  86         {       2700, SDRAM, 0x800000,
  87                 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
  88                 0x82010102, 0x48803800, 0x005E0179,
  89                 0x50, 0x25
  90         },
  91 #endif
  92         // XPERT98
  93         {       1432,  WRAM, 0x800000,
  94                 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
  95                 0x8000000A, 0x48833800, 0x007F0779,
  96                 0x10, 0x19
  97         }
  98 };
  99
 100 typedef struct {
 101         u8 lcd_reg;
 102         u32 val;
 103 } lcd_tbl_t;
 104
 105 static const lcd_tbl_t lcd_tbl[] = {
 106         { 0x01, 0x000520C0 },
 107         { 0x08, 0x02000408 },
 108         { 0x03, 0x00000F00 },
 109         { 0x00, 0x00000000 },
 110         { 0x02, 0x00000000 },
 111         { 0x04, 0x00000000 },
 112         { 0x05, 0x00000000 },
 113         { 0x06, 0x00000000 },
 114         { 0x33, 0x00000000 },
 115         { 0x34, 0x00000000 },
 116         { 0x35, 0x00000000 },
 117         { 0x36, 0x00000000 },
 118         { 0x37, 0x00000000 }
 119 };
 120
 121 static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)
 122 {
 123         aty_st_8(LCD_INDEX, lcd_reg, info);
 124         return aty_ld_le32(LCD_DATA, info);
 125 }
 126
 127 static inline void aty_st_lcd(u8 lcd_reg, u32 val,
 128                               struct fb_info_aty *info)
 129 {
 130         aty_st_8(LCD_INDEX, lcd_reg, info);
 131         aty_st_le32(LCD_DATA, val, info);
 132 }
 133
 134 static void reset_gui(struct fb_info_aty *info)
 135 {
 136         aty_st_8(GEN_TEST_CNTL+1, 0x01, info);
 137         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 138         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 139         mdelay(5);
 140 }
 141
 142
 143 static void reset_sdram(struct fb_info_aty *info)
 144 {
 145         u8 temp;
 146
 147         temp = aty_ld_8(EXT_MEM_CNTL, info);
 148         temp |= 0x02;
 149         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b
 150         temp |= 0x08;
 151         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 10b
 152         temp |= 0x0c;
 153         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 11b
 154         mdelay(5);
 155         temp &= 0xf3;
 156         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 00b
 157         temp &= 0xfd;
 158         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST  = 0b
 159         mdelay(5);
 160 }
 161
 162 static void init_dll(struct fb_info_aty *info)
 163 {
 164         // enable DLL
 165         aty_st_pll(PLL_GEN_CNTL,
 166                    aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,
 167                    info);
 168
 169         // reset DLL
 170         aty_st_pll(DLL_CNTL, 0x82, info);
 171         aty_st_pll(DLL_CNTL, 0xE2, info);
 172         mdelay(5);
 173         aty_st_pll(DLL_CNTL, 0x82, info);
 174         mdelay(6);
 175 }
 176
 177 static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,
 178                          int hsync_enb)
 179 {
 180         reset_gui(info);
 181         aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
 182         aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);
 183
 184         mdelay(15);
 185         init_dll(info);
 186         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 187         mdelay(5);
 188         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 189         mdelay(6);
 190         reset_sdram(info);
 191         aty_st_8(CRTC_GEN_CNTL+3,
 192                  hsync_enb ? 0x00 : 0x04, info);
 193
 194         aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);
 195         aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
 196         aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
 197 }
 198
 199 static int atyfb_xl_init(struct fb_info_aty *info)
 200 {
 201         int i, err;
 202         u32 temp;
 203         union aty_pll pll;
 204         const struct xl_card_cfg_t * card = &card_cfg[xl_card];
 205
 206         aty_st_8(CONFIG_STAT0, 0x85, info);
 207         mdelay(10);
 208
 209         /*
 210          * The following needs to be set before the call
 211          * to var_to_pll() below. They'll be re-set again
 212          * to the same values in aty_init().
 213          */
 214         info->ref_clk_per = 100000000UL/card->ref_crystal;
 215         info->ram_type = card->mem_type;
 216         info->total_vram = card->mem_size;
 217 #if HAS_VICTORIA == 1
 218         if (xl_card == VICTORIA) {
 219                 // the MCLK, XCLK are 120MHz on victoria card
 220                 info->mclk_per = 1000000/120;
 221                 info->xclk_per = 1000000/120;
 222                 info->features &= ~M64F_MFB_TIMES_4;
 223         }
 224 #endif
 225
 226         /*
 227          * Calculate mclk and xclk dividers, etc. The passed
 228          * pixclock and bpp values don't matter yet, the vclk
 229          * isn't programmed until later.
 230          */
 231         if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;
 232 //        if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
 233
 234
 235         aty_st_pll(LVDS_CNTL0, 0x00, info);
 236         aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);
 237         aty_st_pll(V2PLL_CNTL, 0x10, info);
 238         aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);
 239         aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);
 240         aty_st_pll(PLL_VCLK_CNTL, 0x00, info);
 241         aty_st_pll(VFC_CNTL, 0x1B, info);
 242         aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);
 243         aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
 244         aty_st_pll(SPLL_CNTL2, 0x03, info);
 245         aty_st_pll(PLL_GEN_CNTL, 0x44, info);
 246
 247         reset_clocks(info, &pll.ct, 0);
 248         mdelay(10);
 249
 250         aty_st_pll(VCLK_POST_DIV, 0x03, info);
 251         aty_st_pll(VCLK0_FB_DIV, 0xDA, info);
 252         aty_st_pll(VCLK_POST_DIV, 0x0F, info);
 253         aty_st_pll(VCLK1_FB_DIV, 0xF5, info);
 254         aty_st_pll(VCLK_POST_DIV, 0x3F, info);
 255         aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);
 256         aty_st_pll(VCLK2_FB_DIV, 0x00, info);
 257         aty_st_pll(VCLK_POST_DIV, 0xFF, info);
 258         aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);
 259         aty_st_pll(VCLK3_FB_DIV, 0x00, info);
 260
 261         aty_st_8(BUS_CNTL, 0x01, info);
 262         aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
 263
 264         aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
 265         aty_st_le16(CONFIG_STAT0, 0x0020, info);
 266         aty_st_le32(MEM_CNTL, 0x10151A33, info);
 267         aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
 268         aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
 269         aty_st_le32(DAC_CNTL, card->dac_cntl, info);
 270         aty_st_le16(GEN_TEST_CNTL, 0x0100, info);
 271         aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);
 272         aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);
 273
 274         aty_st_le32(HW_DEBUG, card->hw_debug, info);
 275         aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);
 276         aty_st_le16(GP_IO+2, 0x0000, info);
 277         aty_st_le16(GEN_TEST_CNTL, 0x0000, info);
 278         aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);
 279         aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);
 280         aty_st_le32(TIMER_CONFIG, 0x00000000, info);
 281         aty_st_le32(0xEC, 0x00000000, info);
 282         aty_st_le32(0xFC, 0x00000000, info);
 283
 284         for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
 285                 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
 286         }
 287
 288         aty_st_le16(CONFIG_STAT0, 0x00A4, info);
 289         mdelay(10);
 290
 291         aty_st_8(BUS_CNTL+1, 0xA0, info);
 292         mdelay(10);
 293
 294         reset_clocks(info, &pll.ct, 1);
 295         mdelay(10);
 296
 297         // something about power management
 298         aty_st_8(LCD_INDEX, 0x08, info);
 299         aty_st_8(LCD_DATA, 0x0A, info);
 300         aty_st_8(LCD_INDEX, 0x08, info);
 301         aty_st_8(LCD_DATA+3, 0x02, info);
 302         aty_st_8(LCD_INDEX, 0x08, info);
 303         aty_st_8(LCD_DATA, 0x0B, info);
 304         mdelay(2);
 305
 306         // enable display requests, enable CRTC
 307         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 308         // disable display
 309         aty_st_8(CRTC_GEN_CNTL, 0x40, info);
 310         // disable display requests, disable CRTC
 311         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 312         mdelay(10);
 313
 314         aty_st_pll(PLL_YCLK_CNTL, 0x25, info);
 315
 316         aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);
 317         aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);
 318         aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);
 319         aty_st_8(CUSTOM_MACRO_CNTL+1,
 320                  (card->custom_macro_cntl>>8) & 0xff, info);
 321
 322         aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);
 323         aty_st_le32(MEM_CNTL, card->mem_cntl, info);
 324         aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
 325
 326         aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
 327
 328         aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
 329         mdelay(15);
 330         aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);
 331         mdelay(1);
 332
 333         reset_clocks(info, &pll.ct, 0);
 334         mdelay(50);
 335         reset_clocks(info, &pll.ct, 0);
 336         mdelay(50);
 337
 338         // enable extended register block
 339         aty_st_8(BUS_CNTL+3, 0x7B, info);
 340         mdelay(1);
 341         // disable extended register block
 342         aty_st_8(BUS_CNTL+3, 0x73, info);
 343
 344         aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
 345
 346         // disable display requests, disable CRTC
 347         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 348         // disable mapping registers in VGA aperture
 349         aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
 350         mdelay(50);
 351         // enable display requests, enable CRTC
 352         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 353
 354         // make GPIO's 14,15,16 all inputs
 355         aty_st_8(LCD_INDEX, 0x07, info);
 356         aty_st_8(LCD_DATA+3, 0x00, info);
 357
 358         // enable the display
 359         aty_st_8(CRTC_GEN_CNTL, 0x00, info);
 360         mdelay(17);
 361         // reset the memory controller
 362         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 363         mdelay(15);
 364         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 365         mdelay(30);
 366
 367         // enable extended register block
 368         aty_st_8(BUS_CNTL+3,
 369                  (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),
 370                  info);
 371         // set FIFO size to 512 (PIO)
 372         aty_st_le32(GUI_CNTL,
 373                     aty_ld_le32(GUI_CNTL, info) & ~0x3,
 374                     info);
 375
 376         // enable CRT and disable lcd
 377         aty_st_8(LCD_INDEX, 0x01, info);
 378         temp = aty_ld_le32(LCD_DATA, info);
 379         temp = (temp | 0x01) & ~0x02;
 380         aty_st_le32(LCD_DATA, temp, info);
 381
 382         return 0;
 383 }
 384
 385 static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
 386 static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
 387
 388
 389 #if CONFIG_CONSOLE_BTEXT==1
 390 static void aty_set_crtc(const struct fb_info_aty *info,
 391                          const struct crtc *crtc);
 392 static int aty_var_to_crtc(const struct fb_info_aty *info,
 393                            const struct fb_var_screeninfo *var,
 394                            struct crtc *crtc);
 395 #if PLL_CRTC_DECODE==1
 396 static int aty_crtc_to_var(const struct crtc *crtc,
 397                            struct fb_var_screeninfo *var);
 398 #endif
 399
 400 static void atyfb_set_par(const struct atyfb_par *par,
 401                           struct fb_info_aty *info);
 402 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 403                             struct atyfb_par *par,
 404                             const struct fb_info_aty *info);
 405 #if PLL_CRTC_DECODE==1
 406 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 407                             const struct atyfb_par *par,
 408                             const struct fb_info_aty *info);
 409 #endif
 410
 411 static void do_install_cmap(int con, struct fb_info_aty *info);
 412
 413 #if 0
 414 static u32 default_vram  = 0;
 415 #endif
 416
 417 unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7,
 418                                        8,12,10,14, 9,13,11,15 };
 419 #if 0
 420 /* the default colour table, for VGA+ colour systems */
 421 int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa,
 422     0x55,0xff,0x55,0xff,0x55,0xff,0x55,0xff};
 423 int default_grn[] = {0x00,0x00,0xaa,0x55,0x00,0x00,0xaa,0xaa,
 424     0x55,0x55,0xff,0xff,0x55,0x55,0xff,0xff};
 425 int default_blu[] = {0x00,0x00,0x00,0x00,0xaa,0xaa,0xaa,0xaa,
 426     0x55,0x55,0x55,0x55,0xff,0xff,0xff,0xff};
 427 #endif
 428
 429 struct fb_var_screeninfo default_var = {
 430         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 431         640, 480, 640, 480, 0, 0, 8, 0,
 432         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 433         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 434         0, FB_VMODE_NONINTERLACED
 435 };
 436
 437 #endif /*CONFIG_CONSOLE_BTEXT*/
 438
 439 static struct {
 440         u16 pci_id, chip_type;
 441         u8 rev_mask, rev_val;
 442         const char *name;
 443         int pll, mclk, xclk;
 444         u32 features;
 445 } aty_chips[] = {
 446         /* 3D RAGE XL PCI-66/BGA */
 447         { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 448         /* 3D RAGE XL PCI-33/BGA */
 449         { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 450 };
 451 #if CONFIG_CONSOLE_BTEXT==1
 452 static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
 453 {
 454         int i, size;
 455 #if 0
 456         const int ragepro_tbl[] = {
 457                 44, 50, 55, 66, 75, 80, 100
 458         };
 459 #endif
 460         const int ragexl_tbl[] = {
 461                 50, 66, 75, 83, 90, 95, 100, 105,
 462                 110, 115, 120, 125, 133, 143, 166
 463         };
 464         const int *refresh_tbl;
 465 #if 0
 466         if (IS_XL(id)) {
 467 #endif
 468                 refresh_tbl = ragexl_tbl;
 469                 size = sizeof(ragexl_tbl)/sizeof(int);
 470 #if 0
 471         } else {
 472                 refresh_tbl = ragepro_tbl;
 473                 size = sizeof(ragepro_tbl)/sizeof(int);
 474         }
 475 #endif
 476
 477         for (i=0; i < size; i++) {
 478                 if (xclk < refresh_tbl[i])
 479                         break;
 480         }
 481
 482         info->mem_refresh_rate = i;
 483 }
 484 #endif /*CONFIG_CONSOLE_BTEXT */
 485 static void ati_ragexl_init(device_t dev)
 486 {
 487         u32 chip_id;
 488         u32 i;
 489         int j;
 490         u16 type;
 491         u8 rev;
 492         const char *chipname = NULL, *xtal;
 493         int pll, mclk, xclk;
 494
 495 #if CONFIG_CONSOLE_BTEXT==1
 496
 497 #if 0
 498         int gtb_memsize, k;
 499 #endif
 500
 501         struct fb_var_screeninfo var;
 502 #if 0
 503         struct display *disp;
 504 #endif
 505
 506 #if 0
 507         u8 pll_ref_div;
 508 #endif
 509
 510 #endif /*CONFIG_CONSOLE_BTEXT==1 */
 511
 512         struct fb_info_aty *info;
 513         struct fb_info_aty info_t;
 514         struct resource *res;
 515         info = &info_t;
 516
 517 #define USE_AUX_REG 1
 518
 519
 520         res = &dev->resource[0];
 521         if(res->flags & IORESOURCE_IO) {
 522                 res = &dev->resource[1];
 523         }
 524
 525 #if CONFIG_CONSOLE_BTEXT==1
 526         info->frame_buffer = res->base;
 527 #endif /* CONFIG_CONSOLE_BTEXT */
 528
 529 #if USE_AUX_REG==0
 530         info->ati_regbase = res->base+0x7ff000+0xc00;
 531 #else
 532         res = &dev->resource[2];
 533         if(res->flags & IORESOURCE_MEM) {
 534                 info->ati_regbase = res->base+0x400; //using auxiliary register
 535         }
 536
 537 #endif
 538
 539 #if CONFIG_CONSOLE_BTEXT==1
 540         info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
 541 #endif
 542
 543 #if 0
 544         printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
 545 #endif
 546
 547         chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
 548         type = chip_id & CFG_CHIP_TYPE;
 549         rev = (chip_id & CFG_CHIP_REV)>>24;
 550         for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
 551                 if (type == aty_chips[j].chip_type &&
 552                         (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
 553                         chipname = aty_chips[j].name;
 554                         pll = aty_chips[j].pll;
 555                         mclk = aty_chips[j].mclk;
 556                         xclk = aty_chips[j].xclk;
 557                         info->features = aty_chips[j].features;
 558                         goto found;
 559         }
 560         printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
 561         return ;
 562
 563 found:
 564         printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
 565 #if 0
 566         if (M64_HAS(INTEGRATED)) {
 567                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
 568                 if (mclk == 67 && info->ram_type < SDRAM)
 569                         mclk = 63;
 570         }
 571 #endif
 572 #if CONFIG_CONSOLE_BTEXT==1
 573         aty_calc_mem_refresh(info, type, xclk);
 574 #endif /* CONFIG_CONSOLE_BTEXT */
 575
 576         info->pll_per = 1000000/pll;
 577         info->mclk_per = 1000000/mclk;
 578         info->xclk_per = 1000000/xclk;
 579
 580 //        info->dac_ops = &aty_dac_ct;
 581 //        info->pll_ops = &aty_pll_ct;
 582         info->bus_type = PCI;
 583
 584
 585         atyfb_xl_init(info);
 586
 587 #if CONFIG_CONSOLE_BTEXT==1
 588
 589         info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
 590
 591         info->ref_clk_per = 1000000000000ULL/14318180;
 592         xtal = "14.31818";
 593 #if 0
 594         if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) {
 595                 int diff1, diff2;
 596                 diff1 = 510*14/pll_ref_div-pll;
 597                 diff2 = 510*29/pll_ref_div-pll;
 598                 if (diff1 < 0)
 599                         diff1 = -diff1;
 600                 if (diff2 < 0)
 601                         diff2 = -diff2;
 602                 if (diff2 < diff1) {
 603                         info->ref_clk_per = 1000000000000ULL/29498928;
 604                         xtal = "29.498928";
 605                 }
 606         }
 607 #endif
 608
 609     i = aty_ld_le32(MEM_CNTL, info);
 610 #if 0
 611     gtb_memsize = M64_HAS(GTB_DSP);
 612     if (gtb_memsize)  // We have
 613 #endif
 614         switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
 615             case MEM_SIZE_512K:
 616                 info->total_vram = 0x80000;
 617                 break;
 618             case MEM_SIZE_1M:
 619                 info->total_vram = 0x100000;
 620                 break;
 621             case MEM_SIZE_2M_GTB:
 622                 info->total_vram = 0x200000;
 623                 break;
 624             case MEM_SIZE_4M_GTB:
 625                 info->total_vram = 0x400000;
 626                 break;
 627             case MEM_SIZE_6M_GTB:
 628                 info->total_vram = 0x600000;
 629                 break;
 630             case MEM_SIZE_8M_GTB:
 631                 info->total_vram = 0x800000;
 632                 break;
 633             default:
 634                 info->total_vram = 0x80000;
 635         }
 636 #if 0
 637     else
 638         switch (i & MEM_SIZE_ALIAS) {
 639             case MEM_SIZE_512K:
 640                 info->total_vram = 0x80000;
 641                 break;
 642             case MEM_SIZE_1M:
 643                 info->total_vram = 0x100000;
 644                 break;
 645             case MEM_SIZE_2M:
 646                 info->total_vram = 0x200000;
 647                 break;
 648             case MEM_SIZE_4M:
 649                 info->total_vram = 0x400000;
 650                 break;
 651             case MEM_SIZE_6M:
 652                 info->total_vram = 0x600000;
 653                 break;
 654             case MEM_SIZE_8M:
 655                 info->total_vram = 0x800000;
 656                 break;
 657             default:
 658                 info->total_vram = 0x80000;
 659        }
 660 #endif
 661
 662     if (M64_HAS(MAGIC_VRAM_SIZE)) {
 663         if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000)
 664           info->total_vram += 0x400000;
 665     }
 666 #if 0
 667     if (default_vram) {
 668         info->total_vram = default_vram*1024;
 669         i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
 670         if (info->total_vram <= 0x80000)
 671             i |= MEM_SIZE_512K;
 672         else if (info->total_vram <= 0x100000)
 673             i |= MEM_SIZE_1M;
 674         else if (info->total_vram <= 0x200000)
 675             i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
 676         else if (info->total_vram <= 0x400000)
 677             i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
 678         else if (info->total_vram <= 0x600000)
 679             i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
 680         else
 681             i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
 682         aty_st_le32(MEM_CNTL, i, info);
 683     }
 684 #endif
 685
 686     /* Clear the video memory */
 687 //    fb_memset((void *)info->frame_buffer, 0, info->total_vram);
 688 #if 0
 689         disp = &info->disp;
 690
 691 //    strcpy(info->fb_info.modename, atyfb_name);
 692     info->fb_info.node = -1;
 693 //    info->fb_info.fbops = &atyfb_ops;
 694     info->fb_info.disp = disp;
 695 //    strcpy(info->fb_info.fontname, fontname);
 696     info->fb_info.changevar = NULL;
 697 //    info->fb_info.switch_con = &atyfbcon_switch;
 698 //    info->fb_info.updatevar = &atyfbcon_updatevar;
 699 //    info->fb_info.blank = &atyfbcon_blank;
 700     info->fb_info.flags = FBINFO_FLAG_DEFAULT;
 701 #endif
 702         var = default_var;
 703
 704 #if 0
 705     if (noaccel)  // We has noaccel in default
 706         var.accel_flags &= ~FB_ACCELF_TEXT;
 707     else
 708         var.accel_flags |= FB_ACCELF_TEXT;
 709 #endif
 710
 711     if (var.yres == var.yres_virtual) {
 712         u32 vram = info->total_vram ;
 713         var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;
 714         if (var.yres_virtual < var.yres)
 715                 var.yres_virtual = var.yres;
 716     }
 717
 718     if (atyfb_decode_var(&var, &info->default_par, info)) {
 719 #if 0
 720         printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");
 721 #endif
 722         return ;
 723     }
 724 #if 0
 725     for (j = 0; j < 16; j++) {
 726         k = color_table[j];
 727         info->palette[j].red = default_red[k];
 728         info->palette[j].green = default_grn[k];
 729         info->palette[j].blue = default_blu[k];
 730     }
 731 #endif
 732
 733 #if 0
 734     if (curblink && M64_HAS(INTEGRATED)) {
 735         info->cursor = aty_init_cursor(info);
 736         if (info->cursor) {
 737             info->dispsw.cursor = atyfb_cursor;
 738             info->dispsw.set_font = atyfb_set_font;
 739         }
 740     }
 741 #endif
 742
 743 #if PLL_CRTC_DECODE==1
 744         atyfb_set_var(&var, -1, &info->fb_info);
 745 #else
 746             atyfb_set_par(&info->default_par, info);
 747 //            do_install_cmap(-1, &info->fb_info);
 748             do_install_cmap(-1, info);
 749 #endif
 750
 751 #if PLL_CRTC_DECODE==1
 752
 753     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 754                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 755                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 756                          info->current_par.crtc.bpp,
 757                          info->current_par.crtc.vxres*info->default_par.crtc.bpp/8
 758                         );
 759  btext_setup_display(
 760                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 761                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 762                          info->current_par.crtc.bpp,
 763                          info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
 764 #else
 765     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 766                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 767                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 768                          info->default_par.crtc.bpp,
 769                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8
 770                         );
 771  btext_setup_display(
 772                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 773                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 774                          info->default_par.crtc.bpp,
 775                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer);
 776 #endif
 777
 778  btext_clearscreen();
 779
 780  map_boot_text();
 781
 782 #if 0
 783
 784  btext_drawstring("test framebuffer\n");
 785
 786  mdelay(10000);
 787 // test end
 788 #endif
 789
 790 #endif /* CONFIG_CONSOLE_BTEXT */
 791
 792 }
 793
 794 #if CONFIG_CONSOLE_BTEXT==1
 795
 796 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 797                             struct atyfb_par *par,
 798                             const struct fb_info_aty *info)
 799 {
 800     int err;
 801
 802     if ((err = aty_var_to_crtc(info, var, &par->crtc)) ||
 803         (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp,
 804                                          &par->pll)))
 805         return err;
 806
 807 #if 0
 808     if (var->accel_flags & FB_ACCELF_TEXT)
 809         par->accel_flags = FB_ACCELF_TEXT;
 810     else
 811 #endif
 812         par->accel_flags = 0;
 813
 814 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
 815     if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))
 816         return -EINVAL;
 817 #endif
 818
 819     return 0;
 820 }
 821 #if PLL_CRTC_DECODE==1
 822 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 823                             const struct atyfb_par *par,
 824                             const struct fb_info_aty *info)
 825 {
 826     int err;
 827
 828     memset(var, 0, sizeof(struct fb_var_screeninfo));
 829
 830     if ((err = aty_crtc_to_var(&par->crtc, var)))
 831         return err;
 832     var->pixclock = aty_pll_ct_to_var(info, &par->pll);
 833
 834     var->height = -1;
 835     var->width = -1;
 836     var->accel_flags = par->accel_flags;
 837
 838     return 0;
 839 }
 840 #endif
 841 static void aty_set_crtc(const struct fb_info_aty *info,
 842                          const struct crtc *crtc)
 843 {
 844     aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info);
 845     aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info);
 846     aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info);
 847     aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info);
 848     aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info);
 849     aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info);
 850     aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info);
 851 }
 852
 853 static int aty_var_to_crtc(const struct fb_info_aty *info,
 854                            const struct fb_var_screeninfo *var,
 855                            struct crtc *crtc)
 856 {
 857     u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 858     u32 left, right, upper, lower, hslen, vslen, sync, vmode;
 859     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 860     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 861     u32 pix_width, dp_pix_width, dp_chain_mask;
 862
 863     /* input */
 864     xres = var->xres;
 865     yres = var->yres;
 866     vxres = var->xres_virtual;
 867     vyres = var->yres_virtual;
 868     xoffset = var->xoffset;
 869     yoffset = var->yoffset;
 870     bpp = var->bits_per_pixel;
 871     left = var->left_margin;
 872     right = var->right_margin;
 873     upper = var->upper_margin;
 874     lower = var->lower_margin;
 875     hslen = var->hsync_len;
 876     vslen = var->vsync_len;
 877     sync = var->sync;
 878     vmode = var->vmode;
 879
 880     /* convert (and round up) and validate */
 881     xres = (xres+7) & ~7;
 882     xoffset = (xoffset+7) & ~7;
 883     vxres = (vxres+7) & ~7;
 884     if (vxres < xres+xoffset)
 885         vxres = xres+xoffset;
 886     h_disp = xres/8-1;
 887     if (h_disp > 0xff)
 888         FAIL("h_disp too large");
 889     h_sync_strt = h_disp+(right/8);
 890     if (h_sync_strt > 0x1ff)
 891         FAIL("h_sync_start too large");
 892     h_sync_dly = right & 7;
 893     h_sync_wid = (hslen+7)/8;
 894     if (h_sync_wid > 0x1f)
 895         FAIL("h_sync_wid too large");
 896     h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8;
 897     if (h_total > 0x1ff)
 898      FAIL("h_total too large");
 899     h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 900
 901     if (vyres < yres+yoffset)
 902         vyres = yres+yoffset;
 903     v_disp = yres-1;
 904     if (v_disp > 0x7ff)
 905         FAIL("v_disp too large");
 906     v_sync_strt = v_disp+lower;
 907     if (v_sync_strt > 0x7ff)
 908         FAIL("v_sync_strt too large");
 909     v_sync_wid = vslen;
 910     if (v_sync_wid > 0x1f)
 911         FAIL("v_sync_wid too large");
 912     v_total = v_sync_strt+v_sync_wid+upper;
 913     if (v_total > 0x7ff)
 914         FAIL("v_total too large");
 915     v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 916
 917     c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 918
 919     if (bpp <= 8) {
 920         bpp = 8;
 921         pix_width = CRTC_PIX_WIDTH_8BPP;
 922         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 923         dp_chain_mask = 0x8080;
 924     }
 925 #if SUPPORT_8_BPP_ABOVE==1
 926    else if (bpp <= 16) {
 927         bpp = 16;
 928         pix_width = CRTC_PIX_WIDTH_15BPP;
 929         dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 930                        BYTE_ORDER_LSB_TO_MSB;
 931         dp_chain_mask = 0x4210;
 932     } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 933         bpp = 24;
 934         pix_width = CRTC_PIX_WIDTH_24BPP;
 935         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 936         dp_chain_mask = 0x8080;
 937     } else if (bpp <= 32) {
 938         bpp = 32;
 939         pix_width = CRTC_PIX_WIDTH_32BPP;
 940         dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 941                        BYTE_ORDER_LSB_TO_MSB;
 942         dp_chain_mask = 0x8080;
 943     }
 944 #endif
 945 else
 946         FAIL("invalid bpp");
 947
 948     if (vxres*vyres*bpp/8 > info->total_vram)
 949         FAIL("not enough video RAM");
 950   if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 951         FAIL("invalid vmode");
 952
 953     /* output */
 954     crtc->vxres = vxres;
 955     crtc->vyres = vyres;
 956     crtc->xoffset = xoffset;
 957     crtc->yoffset = yoffset;
 958     crtc->bpp = bpp;
 959     crtc->h_tot_disp = h_total | (h_disp<<16);
 960     crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 961                             ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) |
 962                             (h_sync_pol<<21);
 963     crtc->v_tot_disp = v_total | (v_disp<<16);
 964     crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 965     crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 966     crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;
 967     if (M64_HAS(MAGIC_FIFO)) {
 968         /* Not VTB/GTB */
 969         /* FIXME: magic FIFO values */
 970         crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000;
 971     }
 972     crtc->dp_pix_width = dp_pix_width;
 973     crtc->dp_chain_mask = dp_chain_mask;
 974
 975     return 0;
 976 }
 977 #if PLL_CRTC_DECODE==1
 978 static int aty_crtc_to_var(const struct crtc *crtc,
 979                            struct fb_var_screeninfo *var)
 980 {
 981     u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
 982     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 983     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 984     u32 pix_width;
 985
 986     /* input */
 987     h_total = crtc->h_tot_disp & 0x1ff;
 988     h_disp = (crtc->h_tot_disp>>16) & 0xff;
 989     h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
 990                   ((crtc->h_sync_strt_wid>>4) & 0x100);
 991     h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;
 992     h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;
 993     h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;
 994     v_total = crtc->v_tot_disp & 0x7ff;
 995     v_disp = (crtc->v_tot_disp>>16) & 0x7ff;
 996     v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
 997     v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;
 998     v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;
 999     c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1000     pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1001
1002     /* convert */
1003     xres = (h_disp+1)*8;
1004     yres = v_disp+1;
1005     left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly;
1006     right = (h_sync_strt-h_disp)*8+h_sync_dly;
1007     hslen = h_sync_wid*8;
1008     upper = v_total-v_sync_strt-v_sync_wid;
1009     lower = v_sync_strt-v_disp;
1010     vslen = v_sync_wid;
1011     sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1012            (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1013            (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1014
1015     switch (pix_width) {
1016 #if 0
1017         case CRTC_PIX_WIDTH_4BPP:
1018             bpp = 4;
1019             var->red.offset = 0;
1020             var->red.length = 8;
1021             var->green.offset = 0;
1022             var->green.length = 8;
1023             var->blue.offset = 0;
1024             var->blue.length = 8;
1025             var->transp.offset = 0;
1026             var->transp.length = 0;
1027             break;
1028 #endif
1029         case CRTC_PIX_WIDTH_8BPP:
1030             bpp = 8;
1031             var->red.offset = 0;
1032             var->red.length = 8;
1033             var->green.offset = 0;
1034             var->green.length = 8;
1035             var->blue.offset = 0;
1036             var->blue.length = 8;
1037             var->transp.offset = 0;
1038             var->transp.length = 0;
1039             break;
1040 #if SUPPORT_8_BPP_ABOVE==1
1041         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1042             bpp = 16;
1043             var->red.offset = 10;
1044             var->red.length = 5;
1045             var->green.offset = 5;
1046             var->green.length = 5;
1047             var->blue.offset = 0;
1048             var->blue.length = 5;
1049             var->transp.offset = 0;
1050             var->transp.length = 0;
1051             break;
1052         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1053             bpp = 16;
1054             var->red.offset = 11;
1055             var->red.length = 5;
1056             var->green.offset = 5;
1057             var->green.length = 6;
1058             var->blue.offset = 0;
1059             var->blue.length = 5;
1060             var->transp.offset = 0;
1061             var->transp.length = 0;
1062             break;
1063         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1064             bpp = 24;
1065             var->red.offset = 16;
1066             var->red.length = 8;
1067             var->green.offset = 8;
1068             var->green.length = 8;
1069             var->blue.offset = 0;
1070             var->blue.length = 8;
1071            var->transp.offset = 0;
1072             var->transp.length = 0;
1073             break;
1074         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1075             bpp = 32;
1076             var->red.offset = 16;
1077             var->red.length = 8;
1078             var->green.offset = 8;
1079             var->green.length = 8;
1080             var->blue.offset = 0;
1081             var->blue.length = 8;
1082             var->transp.offset = 24;
1083             var->transp.length = 8;
1084             break;
1085 #endif
1086         default:
1087             FAIL("Invalid pixel width");
1088     }
1089
1090     /* output */
1091     var->xres = xres;
1092     var->yres = yres;
1093     var->xres_virtual = crtc->vxres;
1094     var->yres_virtual = crtc->vyres;
1095     var->bits_per_pixel = bpp;
1096     var->xoffset = crtc->xoffset;
1097     var->yoffset = crtc->yoffset;
1098     var->left_margin = left;
1099     var->right_margin = right;
1100     var->upper_margin = upper;
1101     var->lower_margin = lower;
1102     var->hsync_len = hslen;
1103     var->vsync_len = vslen;
1104     var->sync = sync;
1105     var->vmode = FB_VMODE_NONINTERLACED;
1106
1107     return 0;
1108 }
1109 #endif
1110
1111 #if 0
1112 static int encode_fix(struct fb_fix_screeninfo *fix,
1113                       const struct atyfb_par *par,
1114                       const struct fb_info_aty *info)
1115 {
1116     memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1117
1118    // strcpy(fix->id, atyfb_name);
1119          memcpy(fix->id, "atyfb", 5);
1120     fix->smem_start = info->frame_buffer;
1121     fix->smem_len = (u32)info->total_vram;
1122
1123     /*
1124      *  Reg Block 0 (CT-compatible block) is at ati_regbase_phys
1125      *  Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400
1126      */
1127     if (M64_HAS(GX)) {
1128         fix->mmio_start = info->ati_regbase;
1129         fix->mmio_len = 0x400;
1130         fix->accel = FB_ACCEL_ATI_MACH64GX;
1131     } else if (M64_HAS(CT)) {
1132         fix->mmio_start = info->ati_regbase;
1133         fix->mmio_len = 0x400;
1134         fix->accel = FB_ACCEL_ATI_MACH64CT;
1135     } else if (M64_HAS(VT)) {
1136         fix->mmio_start = info->ati_regbase-0x400;
1137         fix->mmio_len = 0x800;
1138         fix->accel = FB_ACCEL_ATI_MACH64VT;
1139     } else /* if (M64_HAS(GT)) */ {
1140         fix->mmio_start = info->ati_regbase-0x400;
1141         fix->mmio_len = 0x800;
1142         fix->accel = FB_ACCEL_ATI_MACH64GT;
1143     }
1144     fix->type = FB_TYPE_PACKED_PIXELS;
1145     fix->type_aux = 0;
1146     fix->line_length = par->crtc.vxres*par->crtc.bpp/8;
1147     fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1148                                      : FB_VISUAL_DIRECTCOLOR;
1149     fix->ywrapstep = 0;
1150     fix->xpanstep = 8;
1151     fix->ypanstep = 1;
1152
1153     return 0;
1154 }
1155 #endif
1156    /*
1157      *  Set the User Defined Part of the Display
1158      */
1159 #if PLL_CRTC_DECODE==1
1160 static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
1161                          struct fb_info *fb)
1162 {
1163     struct fb_info_aty *info = (struct fb_info_aty *)fb;
1164     struct atyfb_par par;
1165 #if 0
1166     struct display *display;
1167     int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel;
1168 #endif
1169     int err;
1170     int activate = var->activate;
1171
1172 #if 0
1173     if (con >= 0)
1174         display = &fb_display[con];
1175     else
1176 #endif
1177 #if 0
1178         display = fb->disp;     /* used during initialization */
1179 #endif
1180
1181     if ((err = atyfb_decode_var(var, &par, info)))
1182         return err;
1183
1184     atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
1185
1186 #if 0
1187     printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
1188 #endif
1189
1190     if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1191 #if 0
1192         oldxres = display->var.xres;
1193         oldyres = display->var.yres;
1194         oldvxres = display->var.xres_virtual;
1195         oldvyres = display->var.yres_virtual;
1196         oldbpp = display->var.bits_per_pixel;
1197         oldaccel = display->var.accel_flags;
1198         display->var = *var;
1199         accel = var->accel_flags & FB_ACCELF_TEXT;
1200         if (oldxres != var->xres || oldyres != var->yres ||
1201             oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1202             oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1203             struct fb_fix_screeninfo fix;
1204
1205             encode_fix(&fix, &par, info);
1206             display->screen_base = (char *)info->frame_buffer;
1207             display->visual = fix.visual;
1208             display->type = fix.type;
1209             display->type_aux = fix.type_aux;
1210             display->ypanstep = fix.ypanstep;
1211             display->ywrapstep = fix.ywrapstep;
1212             display->line_length = fix.line_length;
1213             display->can_soft_blank = 1;
1214             display->inverse = 0;
1215 #if 0
1216            if (accel)
1217                 display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0;
1218             else
1219 #endif
1220                 display->scrollmode = SCROLL_YREDRAW;
1221 #if 0
1222             if (info->fb_info.changevar)
1223                 (*info->fb_info.changevar)(con);
1224 #endif
1225         }
1226 #endif
1227 //        if (!info->fb_info.display_fg ||
1228 //            info->fb_info.display_fg->vc_num == con) {
1229             atyfb_set_par(&par, info);
1230 #if 0
1231             atyfb_set_dispsw(display, info, par.crtc.bpp, accel);
1232 #endif
1233 //        }
1234 #if 0
1235         if (oldbpp != var->bits_per_pixel) {
1236             if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1237                 return err;
1238 #endif
1239             do_install_cmap(con, info);
1240 #if 0
1241         }
1242 #endif
1243     }
1244
1245     return 0;
1246 }
1247
1248 #endif
1249 /* ------------------------------------------------------------------------- */
1250
1251 static void atyfb_set_par(const struct atyfb_par *par,
1252                           struct fb_info_aty *info)
1253 {
1254     u32 i;
1255     int accelmode;
1256     u8 tmp;
1257
1258     accelmode = par->accel_flags;  /* hack */
1259
1260 #if PLL_CRTC_DECODE==1
1261     info->current_par = *par;
1262 #endif
1263
1264     if (info->blitter_may_be_busy)
1265         wait_for_idle(info);
1266     tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);
1267     aty_set_crtc(info, &par->crtc);
1268     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info);
1269                                         /* better call aty_StrobeClock ?? */
1270     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info);
1271
1272     //info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode);
1273     //info->pll_ops->set_pll(info, &par->pll);
1274    aty_set_pll_ct(info, &par->pll);
1275
1276
1277     if (!M64_HAS(INTEGRATED)) {
1278         /* Don't forget MEM_CNTL */
1279         i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff;
1280         switch (par->crtc.bpp) {
1281             case 8:
1282                 i |= 0x02000000;
1283                 break;
1284 #if SUPPORT_8_BPP_ABOVE==1
1285             case 16:
1286                 i |= 0x03000000;
1287                 break;
1288             case 32:
1289                 i |= 0x06000000;
1290                 break;
1291 #endif
1292         }
1293         aty_st_le32(MEM_CNTL, i, info);
1294     } else {
1295         i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff;
1296         if (!M64_HAS(MAGIC_POSTDIV))
1297                 i |= info->mem_refresh_rate << 20;
1298         switch (par->crtc.bpp) {
1299             case 8:
1300 #if SUPPORT_8_BPP_ABOVE==1
1301             case 24:
1302 #endif
1303                 i |= 0x00000000;
1304                break;
1305 #if SUPPORT_8_BPP_ABOVE==1
1306             case 16:
1307                 i |= 0x04000000;
1308                 break;
1309             case 32:
1310                 i |= 0x08000000;
1311                 break;
1312 #endif
1313         }
1314         if (M64_HAS(CT_BUS)) {
1315             aty_st_le32(DAC_CNTL, 0x87010184, info);
1316             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1317         } else if (M64_HAS(VT_BUS)) {
1318             aty_st_le32(DAC_CNTL, 0x87010184, info);
1319             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1320         }  else if (M64_HAS(MOBIL_BUS)) {
1321             aty_st_le32(DAC_CNTL, 0x80010102, info);
1322             aty_st_le32(BUS_CNTL, 0x7b33a040, info);
1323         }  else {
1324             /* GT */
1325             aty_st_le32(DAC_CNTL, 0x86010102, info);
1326             aty_st_le32(BUS_CNTL, 0x7b23a040, info);
1327             aty_st_le32(EXT_MEM_CNTL,
1328                         aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info);
1329         }
1330
1331         aty_st_le32(MEM_CNTL, i, info);
1332     }
1333     aty_st_8(DAC_MASK, 0xff, info);
1334
1335     /* Initialize the graphics engine */
1336 #if 0
1337     if (par->accel_flags & FB_ACCELF_TEXT)
1338         aty_init_engine(par, info);
1339 #endif
1340
1341
1342 }
1343 #if 0
1344 static u16 red2[] = {
1345     0x0000, 0xaaaa
1346 };
1347 static u16 green2[] = {
1348     0x0000, 0xaaaa
1349 };
1350 static u16 blue2[] = {
1351     0x0000, 0xaaaa
1352 };
1353
1354 static u16 red4[] = {
1355     0x0000, 0xaaaa, 0x5555, 0xffff
1356 };
1357 static u16 green4[] = {
1358     0x0000, 0xaaaa, 0x5555, 0xffff
1359 };
1360 static u16 blue4[] = {
1361     0x0000, 0xaaaa, 0x5555, 0xffff
1362 };
1363
1364 static u16 red8[] = {
1365     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
1366 };
1367 static u16 green8[] = {
1368     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa
1369 };
1370 static u16 blue8[] = {
1371     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa
1372 };
1373 #endif
1374 static u16 red16[] = {
1375     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
1376     0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff
1377 };
1378 static u16 green16[] = {
1379     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,
1380     0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff
1381 };
1382 static u16 blue16[] = {
1383     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,
1384     0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff
1385 };
1386 #if 0
1387 static struct fb_cmap default_2_colors = {
1388     0, 2, red2, green2, blue2, NULL
1389 };
1390 static struct fb_cmap default_8_colors = {
1391     0, 8, red8, green8, blue8, NULL
1392 };
1393 static struct fb_cmap default_4_colors = {
1394     0, 4, red4, green4, blue4, NULL
1395 };
1396 #endif
1397 static struct fb_cmap default_16_colors = {
1398     0, 16, red16, green16, blue16, NULL
1399 };
1400
1401
1402
1403 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1404                            u_int transp, struct fb_info_aty *info)
1405 {
1406     int i, scale;
1407
1408     if (regno > 255)
1409         return 1;
1410     red >>= 8;
1411     green >>= 8;
1412     blue >>= 8;
1413 #if 0
1414 //We don't need to store it
1415     info->palette[regno].red = red;
1416     info->palette[regno].green = green;
1417     info->palette[regno].blue = blue;
1418 #endif
1419     i = aty_ld_8(DAC_CNTL, info) & 0xfc;
1420     if (M64_HAS(EXTRA_BRIGHT))
1421         i |= 0x2;       /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
1422     aty_st_8(DAC_CNTL, i, info);
1423     aty_st_8(DAC_MASK, 0xff, info);
1424 #if PLL_CRTC_DECODE==1
1425     scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;
1426 #else
1427     scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
1428 #endif
1429     writeb(regno << scale, &info->aty_cmap_regs->windex);
1430     writeb(red, &info->aty_cmap_regs->lut);
1431     writeb(green, &info->aty_cmap_regs->lut);
1432     writeb(blue, &info->aty_cmap_regs->lut);
1433     return 0;
1434 }
1435
1436 int fb_set_cmap(struct fb_cmap *cmap, int kspc,
1437                 int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,
1438                                  struct fb_info_aty *),
1439                 struct fb_info_aty *info)
1440 {
1441     int i, start;
1442     u16 *red, *green, *blue, *transp;
1443     u_int hred, hgreen, hblue, htransp;
1444
1445     red = cmap->red;
1446     green = cmap->green;
1447     blue = cmap->blue;
1448     transp = cmap->transp;
1449     start = cmap->start;
1450
1451     if (start < 0)
1452         return -EINVAL;
1453     for (i = 0; i < cmap->len; i++) {
1454             hred = *red;
1455             hgreen = *green;
1456             hblue = *blue;
1457             htransp = transp ? *transp : 0;
1458         red++;
1459         green++;
1460         blue++;
1461         if (transp)
1462             transp++;
1463         if (setcolreg(start++, hred, hgreen, hblue, htransp, info))
1464             return 0;
1465     }
1466     return 0;
1467 }
1468
1469 struct fb_cmap *fb_default_cmap(int len)
1470 {
1471 #if 0
1472     if (len <= 2)
1473         return &default_2_colors;
1474     if (len <= 4)
1475         return &default_4_colors;
1476     if (len <= 8)
1477         return &default_8_colors;
1478 #endif
1479     return &default_16_colors;
1480 }
1481
1482 static void do_install_cmap(int con, struct fb_info_aty *info)
1483 {
1484 #if PLL_CRTC_DECODE==1
1485         int size = info->current_par.crtc.bpp == 16 ? 32 : 256;
1486 #else
1487         int size = 256;
1488 #endif
1489         fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);
1490 }
1491
1492 #endif /*CONFIG_CONSOLE_BTEXT */
1493
1494 static struct device_operations ati_ragexl_graph_ops  = {
1495         .read_resources   = pci_dev_read_resources,
1496         .set_resources    = pci_dev_set_resources,
1497         .enable_resources = pci_dev_enable_resources,
1498         .init             = ati_ragexl_init,
1499         .scan_bus         = 0,
1500 };
1501
1502 static const struct pci_driver ati_ragexl_graph_driver __pci_driver = {
1503         .ops    = &ati_ragexl_graph_ops,
1504         .vendor = PCI_VENDOR_ID_ATI,
1505         .device = PCI_DEVICE_ID_ATI_215XL,
1506 };
1507
1508