2 * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
27 #include <console/console.h>
28 #include <device/device.h>
29 #include <cpu/x86/msr.h>
30 #include <cpu/x86/mtrr.h>
31 #include <cpu/x86/cache.h>
33 #warning "FIXME I do not properly handle address more than 36 physical address bits"
35 # define ADDRESS_BITS 40
37 # define ADDRESS_BITS 36
39 #define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
40 #define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
42 static unsigned int mtrr_msr[] = {
43 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
44 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
45 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
49 static void enable_fixed_mtrr(void)
53 msr = rdmsr(MTRRdefType_MSR);
55 wrmsr(MTRRdefType_MSR, msr);
58 static void enable_var_mtrr(void)
62 msr = rdmsr(MTRRdefType_MSR);
64 wrmsr(MTRRdefType_MSR, msr);
67 /* setting variable mtrr, comes from linux kernel source */
68 static void set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
72 base.hi = basek >> 22;
73 base.lo = basek << 10;
75 //printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
77 if (sizek < 4*1024*1024) {
78 mask.hi = ADDRESS_MASK_HIGH;
79 mask.lo = ~((sizek << 10) -1);
82 mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
89 // it is recommended that we disable and enable cache when we
94 zero.lo = zero.hi = 0;
95 /* The invalid bit is kept in the mask, so we simply clear the
96 relevant mask register to disable a range. */
97 wrmsr (MTRRphysMask_MSR(reg), zero);
99 /* Bit 32-35 of MTRRphysMask should be set to 1 */
102 wrmsr (MTRRphysBase_MSR(reg), base);
103 wrmsr (MTRRphysMask_MSR(reg), mask);
108 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
109 static inline unsigned int fms(unsigned int x)
113 __asm__("bsrl %1,%0\n\t"
116 "1:" : "=r" (r) : "g" (x));
120 /* fms: find least sigificant bit set */
121 static inline unsigned int fls(unsigned int x)
125 __asm__("bsfl %1,%0\n\t"
128 "1:" : "=r" (r) : "g" (x));
132 /* setting up variable and fixed mtrr
134 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
135 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
136 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
137 * requirement. So a 8K range must be 8K aligned not 4K aligned.
139 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
140 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
141 * A 124MB (128MB - 4MB SMA) example:
142 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
143 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
145 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
146 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
147 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
148 * The same 124MB example:
149 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
150 * or a 156MB (128MB + 32MB - 4MB SMA) example:
151 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
153 /* 2 MTRRS are reserved for the operating system */
161 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
164 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
167 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
169 msr.lo = msr.hi = 0; /* Shut up gcc */
170 for(i = first; i < last; i++) {
171 /* When I switch to a new msr read it in */
172 if (fixed_msr != i >> 3) {
173 /* But first write out the old msr */
174 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
176 wrmsr(mtrr_msr[fixed_msr], msr);
180 msr = rdmsr(mtrr_msr[fixed_msr]);
183 msr.lo &= ~(0xff << ((i&3)*8));
184 msr.lo |= type << ((i&3)*8);
186 msr.hi &= ~(0xff << ((i&3)*8));
187 msr.hi |= type << ((i&3)*8);
190 /* Write out the final msr */
191 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
193 wrmsr(mtrr_msr[fixed_msr], msr);
198 static unsigned fixed_mtrr_index(unsigned long addrk)
201 index = (addrk - 0) >> 6;
203 index = ((addrk - 8*64) >> 4) + 8;
206 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
208 if (index > NUM_FIXED_RANGES) {
209 index = NUM_FIXED_RANGES;
214 static unsigned int range_to_mtrr(unsigned int reg,
215 unsigned long range_startk, unsigned long range_sizek,
216 unsigned long next_range_startk)
218 if (!range_sizek || (reg >= BIOS_MTRRS)) {
222 unsigned long max_align, align;
224 /* Compute the maximum size I can make a range */
225 max_align = fls(range_startk);
226 align = fms(range_sizek);
227 if (align > max_align) {
231 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
232 reg, range_startk >>10, sizek >> 10);
233 set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
234 range_startk += sizek;
235 range_sizek -= sizek;
236 if (reg >= BIOS_MTRRS)
242 static unsigned long resk(uint64_t value)
244 unsigned long resultk;
245 if (value < (1ULL << 42)) {
246 resultk = value >> 10;
249 resultk = 0xffffffff;
254 static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
256 unsigned int start_mtrr;
257 unsigned int last_mtrr;
258 start_mtrr = fixed_mtrr_index(resk(res->base));
259 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
260 if (start_mtrr >= NUM_FIXED_RANGES) {
263 printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
264 start_mtrr, last_mtrr);
265 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
269 struct var_mtrr_state {
270 unsigned long range_startk, range_sizek;
274 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
276 struct var_mtrr_state *state = gp;
277 unsigned long basek, sizek;
278 if (state->reg >= BIOS_MTRRS)
280 basek = resk(res->base);
281 sizek = resk(res->size);
282 /* See if I can merge with the last range
283 * Either I am below 1M and the fixed mtrrs handle it, or
286 if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) {
287 unsigned long endk = basek + sizek;
288 state->range_sizek = endk - state->range_startk;
291 /* Write the range mtrrs */
292 if (state->range_sizek != 0) {
293 state->reg = range_to_mtrr(state->reg, state->range_startk, state->range_sizek, basek);
294 state->range_startk = 0;
295 state->range_sizek = 0;
297 /* Allocate an msr */
298 state->range_startk = basek;
299 state->range_sizek = sizek;
302 void x86_setup_mtrrs(void)
304 /* Try this the simple way of incrementally adding together
305 * mtrrs. If this doesn't work out we can get smart again
306 * and clear out the mtrrs.
308 struct var_mtrr_state var_state;
311 /* Initialized the fixed_mtrrs to uncached */
312 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
313 0, NUM_FIXED_RANGES);
314 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
316 /* Now see which of the fixed mtrrs cover ram.
318 search_global_resources(
319 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
320 set_fixed_mtrr_resource, NULL);
321 printk_debug("DONE fixed MTRRs\n");
323 /* Cache as many memory areas as possible */
324 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
325 * In some cases it is definitely possible to do better.
327 var_state.range_startk = 0;
328 var_state.range_sizek = 0;
330 search_global_resources(
331 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
332 set_var_mtrr_resource, &var_state);
334 /* Write the last range */
335 var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, var_state.range_sizek, 0);
336 printk_debug("DONE variable MTRRs\n");
337 printk_debug("Clear out the extra MTRR's\n");
338 /* Clear out the extra MTRR's */
339 while(var_state.reg < MTRRS) {
340 set_var_mtrr(var_state.reg++, 0, 0, 0);
342 /* enable fixed MTRR */
343 printk_spew("call enable_fixed_mtrr()\n");
345 printk_spew("call enable_var_mtrr()\n");
347 printk_spew("Leave %s\n", __FUNCTION__);
351 int x86_mtrr_check(void)
353 /* Only Pentium Pro and later have MTRR */
355 printk_debug("\nMTRR check\n");
360 printk_debug("Fixed MTRRs : ");
362 printk_debug("Enabled\n");
364 printk_debug("Disabled\n");
366 printk_debug("Variable MTRRs: ");
368 printk_debug("Enabled\n");
370 printk_debug("Disabled\n");
375 return ((int) msr.lo);