- To reduce confuse rename the parts of linuxbios bios that run from
authorEric Biederman <ebiederm@xmission.com>
Sat, 30 Oct 2004 08:05:41 +0000 (08:05 +0000)
committerEric Biederman <ebiederm@xmission.com>
Sat, 30 Oct 2004 08:05:41 +0000 (08:05 +0000)
commitf8a2dddb573faef41ad43ee111d91d4c5259ad59
tree3606ac56f585bce51868b8a5388bf9d0bb4561b9
parent0afcba7a3d0e7dc22818ecdfd79230f5fb987f0d
- To reduce confuse rename the parts of linuxbios bios that run from
  ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
41 files changed:
src/arch/i386/boot/linuxbios_table.c
src/arch/i386/init/ldscript.lb
src/arch/i386/lib/Config.lb
src/arch/i386/lib/c_start.S
src/arch/i386/llshell/llshell.inc [new file with mode: 0644]
src/arch/i386/llshell/readme.linuxbios [new file with mode: 0644]
src/arch/ppc/init/ldscript.lb
src/config/Config.lb
src/config/Options.lb
src/config/linuxbios_c.ld [deleted file]
src/config/linuxbios_ram.ld [new file with mode: 0644]
src/cpu/amd/model_fxx/Config.lb
src/cpu/amd/mtrr/amd_mtrr.c
src/cpu/amd/socket_940/Config.lb
src/cpu/amd/socket_940/socket_940.c
src/cpu/intel/model_f0x/Config.lb
src/cpu/intel/model_f1x/Config.lb
src/cpu/intel/model_f2x/Config.lb
src/cpu/intel/model_f3x/Config.lb
src/cpu/x86/16bit/reset16.inc
src/cpu/x86/16bit/reset16.lds
src/cpu/x86/lapic/secondary.S
src/cpu/x86/mtrr/earlymtrr.c
src/cpu/x86/mtrr/mtrr.c
src/devices/device.c
src/devices/device_util.c
src/devices/root_device.c
src/include/delay.h
src/include/device/device.h
src/include/device/pci_ids.h
src/include/device/resource.h
src/mainboard/arima/hdama/Config.lb
src/mainboard/arima/hdama/Options.lb
src/mainboard/arima/hdama/mainboard.c
src/northbridge/amd/amdk8/coherent_ht.c
src/northbridge/amd/amdk8/northbridge.c
src/ram/ramtest.c
src/southbridge/amd/amd8111/amd8111.c
src/superio/NSC/pc87360/superio.c
targets/arima/hdama/Config.lb
util/romcc/romcc.c