2 * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
26 #include <console/console.h>
27 #include <device/device.h>
28 #include <cpu/x86/msr.h>
29 #include <cpu/x86/mtrr.h>
30 #include <cpu/x86/cache.h>
32 #warning "FIXME I do not properly handle address more than 36 physical address bits"
34 # define ADDRESS_BITS 40
36 # define ADDRESS_BITS 36
38 #define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
39 #define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
41 static unsigned int mtrr_msr[] = {
42 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
43 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
44 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
48 static void enable_fixed_mtrr(void)
52 msr = rdmsr(MTRRdefType_MSR);
54 wrmsr(MTRRdefType_MSR, msr);
57 static void enable_var_mtrr(void)
61 msr = rdmsr(MTRRdefType_MSR);
63 wrmsr(MTRRdefType_MSR, msr);
66 /* setting variable mtrr, comes from linux kernel source */
67 static void set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
71 base.hi = basek >> 22;
72 base.lo = basek << 10;
74 //printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
76 if (sizek < 4*1024*1024) {
77 mask.hi = ADDRESS_MASK_HIGH;
78 mask.lo = ~((sizek << 10) -1);
81 mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
88 // it is recommended that we disable and enable cache when we
93 zero.lo = zero.hi = 0;
94 /* The invalid bit is kept in the mask, so we simply clear the
95 relevant mask register to disable a range. */
96 wrmsr (MTRRphysMask_MSR(reg), zero);
98 /* Bit 32-35 of MTRRphysMask should be set to 1 */
101 wrmsr (MTRRphysBase_MSR(reg), base);
102 wrmsr (MTRRphysMask_MSR(reg), mask);
107 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
108 static inline unsigned int fms(unsigned int x)
112 __asm__("bsrl %1,%0\n\t"
115 "1:" : "=r" (r) : "g" (x));
119 /* fms: find least sigificant bit set */
120 static inline unsigned int fls(unsigned int x)
124 __asm__("bsfl %1,%0\n\t"
127 "1:" : "=r" (r) : "g" (x));
131 /* setting up variable and fixed mtrr
133 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
134 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
135 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
136 * requirement. So a 8K range must be 8K aligned not 4K aligned.
138 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
139 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
140 * A 124MB (128MB - 4MB SMA) example:
141 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
142 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
144 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
145 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
146 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
147 * The same 124MB example:
148 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
149 * or a 156MB (128MB + 32MB - 4MB SMA) example:
150 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
152 /* 2 MTRRS are reserved for the operating system */
160 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
163 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
166 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
168 msr.lo = msr.hi = 0; /* Shut up gcc */
169 for(i = first; i < last; i++) {
170 /* When I switch to a new msr read it in */
171 if (fixed_msr != i >> 3) {
172 /* But first write out the old msr */
173 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
175 wrmsr(mtrr_msr[fixed_msr], msr);
179 msr = rdmsr(mtrr_msr[fixed_msr]);
182 msr.lo &= ~(0xff << ((i&3)*8));
183 msr.lo |= type << ((i&3)*8);
185 msr.hi &= ~(0xff << ((i&3)*8));
186 msr.hi |= type << ((i&3)*8);
189 /* Write out the final msr */
190 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
192 wrmsr(mtrr_msr[fixed_msr], msr);
197 static unsigned fixed_mtrr_index(unsigned long addrk)
200 index = (addrk - 0) >> 6;
202 index = ((addrk - 8*64) >> 4) + 8;
205 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
207 if (index > NUM_FIXED_RANGES) {
208 index = NUM_FIXED_RANGES;
213 static unsigned int range_to_mtrr(unsigned int reg,
214 unsigned long range_startk, unsigned long range_sizek,
215 unsigned long next_range_startk)
217 if (!range_sizek || (reg >= BIOS_MTRRS)) {
221 unsigned long max_align, align;
223 /* Compute the maximum size I can make a range */
224 max_align = fls(range_startk);
225 align = fms(range_sizek);
226 if (align > max_align) {
230 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
231 reg, range_startk >>10, sizek >> 10);
232 set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
233 range_startk += sizek;
234 range_sizek -= sizek;
235 if (reg >= BIOS_MTRRS)
241 static unsigned long resk(uint64_t value)
243 unsigned long resultk;
244 if (value < (1ULL << 42)) {
245 resultk = value >> 10;
248 resultk = 0xffffffff;
253 void x86_setup_mtrrs(void)
255 /* Try this the simple way of incrementally adding together
256 * mtrrs. If this doesn't work out we can get smart again
257 * and clear out the mtrrs.
260 unsigned long range_startk, range_sizek;
264 /* Initialized the fixed_mtrrs to uncached */
265 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
266 0, NUM_FIXED_RANGES);
267 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
269 /* Now see which of the fixed mtrrs cover ram.
271 for(dev = all_devices; dev; dev = dev->next) {
272 struct resource *res, *last;
273 last = &dev->resource[dev->resources];
274 for(res = &dev->resource[0]; res < last; res++) {
275 unsigned int start_mtrr;
276 unsigned int last_mtrr;
277 if (!(res->flags & IORESOURCE_MEM) ||
278 !(res->flags & IORESOURCE_CACHEABLE))
282 start_mtrr = fixed_mtrr_index(resk(res->base));
283 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
284 if (start_mtrr >= NUM_FIXED_RANGES) {
287 printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
288 start_mtrr, last_mtrr);
289 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
292 printk_debug("DONE fixed MTRRs\n");
293 /* Cache as many memory areas as possible */
294 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
295 * In some cases it is definitely possible to do better.
300 for(dev = all_devices; dev; dev = dev->next) {
301 struct resource *res, *last;
302 last = &dev->resource[dev->resources];
303 for(res = &dev->resource[0]; res < last; res++) {
304 unsigned long basek, sizek;
305 if (!(res->flags & IORESOURCE_MEM) ||
306 !(res->flags & IORESOURCE_CACHEABLE)) {
309 basek = resk(res->base);
310 sizek = resk(res->size);
311 /* See if I can merge with the last range
312 * Either I am below 1M and the fixed mtrrs handle it, or
315 if ((basek <= 1024) || (range_startk + range_sizek == basek)) {
316 unsigned long endk = basek + sizek;
317 range_sizek = endk - range_startk;
320 /* Write the range mtrrs */
321 if (range_sizek != 0) {
322 reg = range_to_mtrr(reg, range_startk, range_sizek, basek);
325 if (reg >= BIOS_MTRRS)
328 /* Allocate an msr */
329 range_startk = basek;
334 /* Write the last range */
335 reg = range_to_mtrr(reg, range_startk, range_sizek, 0);
336 printk_debug("DONE variable MTRRs\n");
337 printk_debug("Clear out the extra MTRR's\n");
338 /* Clear out the extra MTRR's */
340 set_var_mtrr(reg++, 0, 0, 0);
342 /* enable fixed MTRR */
343 printk_spew("call enable_fixed_mtrr()\n");
345 printk_spew("call enable_var_mtrr()\n");
347 printk_spew("Leave %s\n", __FUNCTION__);
351 int x86_mtrr_check(void)
353 /* Only Pentium Pro and later have MTRR */
355 printk_debug("\nMTRR check\n");
360 printk_debug("Fixed MTRRs : ");
362 printk_debug("Enabled\n");
364 printk_debug("Disabled\n");
366 printk_debug("Variable MTRRs: ");
368 printk_debug("Enabled\n");
370 printk_debug("Disabled\n");
375 return ((int) msr.lo);