- Better memory I/O space distinguishing in amd_mtrr.c

  This is way to much code duplication but for now things work.
- Fix the typo in amd8111_lpc.c
- Remove an unused macro, use continue instead of break in mtrr.c

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index ab6bc2bbee830e8e66b293d817bbbdf40cde299d..0247fd00d372ea592f5145dceae64fdd5ce0256b 100644 (file)
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -17,6 +17,66 @@ static unsigned long resk(uint64_t value)
        return resultk;
 }
 
+#if 1
+static unsigned fixed_mtrr_index(unsigned long addrk)
+{
+       unsigned index;
+       index = (addrk - 0) >> 6;
+       if (index >= 8) {
+               index = ((addrk - 8*64) >> 4) + 8;
+       }
+       if (index >= 24) {
+               index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
+       }
+       if (index > NUM_FIXED_RANGES) {
+               index = NUM_FIXED_RANGES;
+       }
+       return index;
+}
+
+
+static unsigned int mtrr_msr[] = {
+       MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
+       MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
+       MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
+};
+
+static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
+{
+       unsigned int i;
+       unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
+       msr_t msr;
+       msr.lo = msr.hi = 0; /* Shut up gcc */
+       for (i = first; i < last; i++) {
+               /* When I switch to a new msr read it in */
+               if (fixed_msr != i >> 3) {
+                       /* But first write out the old msr */
+                       if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
+                               disable_cache();
+                               wrmsr(mtrr_msr[fixed_msr], msr);
+                               enable_cache();
+                       }
+                       fixed_msr = i>>3;
+                       msr = rdmsr(mtrr_msr[fixed_msr]);
+               }
+               if ((i & 7) < 4) {
+                       msr.lo &= ~(0xff << ((i&3)*8));
+                       msr.lo |= type << ((i&3)*8);
+               } else {
+                       msr.hi &= ~(0xff << ((i&3)*8));
+                       msr.hi |= type << ((i&3)*8);
+               }
+       }
+       /* Write out the final msr */
+       if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
+               disable_cache();
+               wrmsr(mtrr_msr[fixed_msr], msr);
+               enable_cache();
+       }
+}
+
+#endif
+
 void amd_setup_mtrrs(void)
 {
        unsigned long mmio_basek, tomk;
@@ -24,12 +84,16 @@ void amd_setup_mtrrs(void)
        device_t dev;
        msr_t msr;
 
-       /* Disable the access to AMD RdDram and WrDram extension bits */
+       /* Enable the access to AMD RdDram and WrDram extension bits */
        msr = rdmsr(SYSCFG_MSR);
-       msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+       msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
        wrmsr(SYSCFG_MSR, msr);
 
-       x86_setup_mtrrs();
+       printk_debug("\n");
+       /* Initialized the fixed_mtrrs to uncached */
+       printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n", 
+               0, NUM_FIXED_RANGES);
+       set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
 
        /* Except for the PCI MMIO hole just before 4GB there are no
         * significant holes in the address space, so just account
@@ -41,6 +105,7 @@ void amd_setup_mtrrs(void)
                last = &dev->resource[dev->resources];
                for(res = &dev->resource[0]; res < last; res++) {
                        unsigned long topk;
+                       unsigned long start_mtrr, last_mtrr;
                        if (!(res->flags & IORESOURCE_MEM) ||
                                (!(res->flags & IORESOURCE_CACHEABLE))) {
                                continue;
@@ -52,8 +117,18 @@ void amd_setup_mtrrs(void)
                        if ((topk < 4*1024*1024) && (mmio_basek < topk)) {
                                mmio_basek = topk;
                        }
+
+                       start_mtrr = fixed_mtrr_index(resk(res->base));
+                       last_mtrr  = fixed_mtrr_index(resk(res->base + res->size));
+                       if (start_mtrr >= NUM_FIXED_RANGES) {
+                               continue;
+                       }
+                       printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
+                               start_mtrr, last_mtrr);
+                       set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
                }
        }
+       printk_debug("DONE fixed MTRRs\n");
        if (mmio_basek > tomk) {
                mmio_basek = tomk;
        }
@@ -82,9 +157,19 @@ void amd_setup_mtrrs(void)
                wrmsr(i, msr);
        }
 
+       /* Enable Variable Mtrrs 
+        * Enable the RdMem and WrMem bits in the fixed mtrrs.
+        * Disable access to the RdMem and WrMem in the fixed mtrr.
+        */
        msr = rdmsr(SYSCFG_MSR);
-       msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_TOM2En;
+       msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_TOM2En;
+       msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
        wrmsr(SYSCFG_MSR, msr);
 
        enable_cache();
+
+       /* Now that I have mapped what is memory and what is not
+        * Setup the mtrrs so we can cache the memory.
+        */
+       x86_setup_mtrrs();
 }

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e38f2373630e194c064180cc457022fa23f7eaf..5ffaaf053fdfc9fac653358eb10d96db23c5a82b 100644 (file)
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -29,8 +29,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 
-#define arraysize(x)   (sizeof(x)/sizeof((x)[0]))
-
 #warning "FIXME I do not properly handle address more than 36 physical address bits"
 #ifdef k8
 # define ADDRESS_BITS 40
@@ -284,7 +282,7 @@ void x86_setup_mtrrs(void)
                        start_mtrr = fixed_mtrr_index(resk(res->base));
                        last_mtrr  = fixed_mtrr_index(resk((res->base + res->size)));
                        if (start_mtrr >= NUM_FIXED_RANGES) {
-                               break;
+                               continue;
                        }
                        printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
                                start_mtrr, last_mtrr);

diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 50025bf2f75d97545c91f8a55c7aa2287291da20..5d3fc44a1b1b8474c40a18869a0115a2fa07dd04 100644 (file)
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -170,7 +170,7 @@ static void amd8111_lpc_read_resources(device_t dev)
        res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
-static void amd8111_lpc_enable_resoruces(device_t dev)
+static void amd8111_lpc_enable_resources(device_t dev)
 {
        pci_dev_enable_resources(dev);
        enable_childrens_resources(dev);