2 * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
27 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed
28 2005.6 Eric add address bit in x86_setup_mtrrs
29 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs,
30 for AMD, it will not use x86_setup_fixed_mtrrs
34 #include <console/console.h>
35 #include <device/device.h>
36 #include <cpu/x86/msr.h>
37 #include <cpu/x86/mtrr.h>
38 #include <cpu/x86/cache.h>
40 static unsigned int mtrr_msr[] = {
41 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
42 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
43 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
47 void enable_fixed_mtrr(void)
51 msr = rdmsr(MTRRdefType_MSR);
53 wrmsr(MTRRdefType_MSR, msr);
56 static void enable_var_mtrr(void)
60 msr = rdmsr(MTRRdefType_MSR);
62 wrmsr(MTRRdefType_MSR, msr);
65 /* setting variable mtrr, comes from linux kernel source */
66 static void set_var_mtrr(
67 unsigned int reg, unsigned long basek, unsigned long sizek,
68 unsigned char type, unsigned address_bits)
71 unsigned address_mask_high;
73 address_mask_high = ((1u << (address_bits - 32u)) - 1u);
75 base.hi = basek >> 22;
76 base.lo = basek << 10;
78 printk_spew("ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
80 if (sizek < 4*1024*1024) {
81 mask.hi = address_mask_high;
82 mask.lo = ~((sizek << 10) -1);
85 mask.hi = address_mask_high & (~((sizek >> 22) -1));
92 // it is recommended that we disable and enable cache when we
97 zero.lo = zero.hi = 0;
98 /* The invalid bit is kept in the mask, so we simply clear the
99 relevant mask register to disable a range. */
100 wrmsr (MTRRphysMask_MSR(reg), zero);
102 /* Bit 32-35 of MTRRphysMask should be set to 1 */
105 wrmsr (MTRRphysBase_MSR(reg), base);
106 wrmsr (MTRRphysMask_MSR(reg), mask);
111 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
112 static inline unsigned int fms(unsigned int x)
116 __asm__("bsrl %1,%0\n\t"
119 "1:" : "=r" (r) : "g" (x));
123 /* fms: find least sigificant bit set */
124 static inline unsigned int fls(unsigned int x)
128 __asm__("bsfl %1,%0\n\t"
131 "1:" : "=r" (r) : "g" (x));
135 /* setting up variable and fixed mtrr
137 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
138 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
139 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
140 * requirement. So a 8K range must be 8K aligned not 4K aligned.
142 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
143 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
144 * A 124MB (128MB - 4MB SMA) example:
145 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
146 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
148 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
149 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
150 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
151 * The same 124MB example:
152 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
153 * or a 156MB (128MB + 32MB - 4MB SMA) example:
154 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
156 /* 2 MTRRS are reserved for the operating system */
164 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
167 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
170 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
172 msr.lo = msr.hi = 0; /* Shut up gcc */
173 for(i = first; i < last; i++) {
174 /* When I switch to a new msr read it in */
175 if (fixed_msr != i >> 3) {
176 /* But first write out the old msr */
177 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
179 wrmsr(mtrr_msr[fixed_msr], msr);
183 msr = rdmsr(mtrr_msr[fixed_msr]);
186 msr.lo &= ~(0xff << ((i&3)*8));
187 msr.lo |= type << ((i&3)*8);
189 msr.hi &= ~(0xff << ((i&3)*8));
190 msr.hi |= type << ((i&3)*8);
193 /* Write out the final msr */
194 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
196 wrmsr(mtrr_msr[fixed_msr], msr);
201 static unsigned fixed_mtrr_index(unsigned long addrk)
204 index = (addrk - 0) >> 6;
206 index = ((addrk - 8*64) >> 4) + 8;
209 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
211 if (index > NUM_FIXED_RANGES) {
212 index = NUM_FIXED_RANGES;
217 static unsigned int range_to_mtrr(unsigned int reg,
218 unsigned long range_startk, unsigned long range_sizek,
219 unsigned long next_range_startk, unsigned char type, unsigned address_bits)
221 if (!range_sizek || (reg >= BIOS_MTRRS)) {
225 unsigned long max_align, align;
227 /* Compute the maximum size I can make a range */
228 max_align = fls(range_startk);
229 align = fms(range_sizek);
230 if (align > max_align) {
234 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n",
235 reg, range_startk >>10, sizek >> 10,
236 (type==MTRR_TYPE_UNCACHEABLE)?"UC":
237 ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
239 set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
240 range_startk += sizek;
241 range_sizek -= sizek;
242 if (reg >= BIOS_MTRRS)
248 static unsigned long resk(uint64_t value)
250 unsigned long resultk;
251 if (value < (1ULL << 42)) {
252 resultk = value >> 10;
255 resultk = 0xffffffff;
260 static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
262 unsigned int start_mtrr;
263 unsigned int last_mtrr;
264 start_mtrr = fixed_mtrr_index(resk(res->base));
265 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
266 if (start_mtrr >= NUM_FIXED_RANGES) {
269 printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
270 start_mtrr, last_mtrr);
271 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
275 struct var_mtrr_state {
276 unsigned long range_startk, range_sizek;
278 unsigned long hole_startk, hole_sizek;
279 unsigned address_bits;
282 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
284 struct var_mtrr_state *state = gp;
285 unsigned long basek, sizek;
286 if (state->reg >= BIOS_MTRRS)
288 basek = resk(res->base);
289 sizek = resk(res->size);
290 /* See if I can merge with the last range
291 * Either I am below 1M and the fixed mtrrs handle it, or
294 if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) {
295 unsigned long endk = basek + sizek;
296 state->range_sizek = endk - state->range_startk;
299 /* Write the range mtrrs */
300 if (state->range_sizek != 0) {
301 if (state->hole_sizek == 0) {
302 /* We need to put that on to hole */
303 unsigned long endk = basek + sizek;
304 state->hole_startk = state->range_startk + state->range_sizek;
305 state->hole_sizek = basek - state->hole_startk;
306 state->range_sizek = endk - state->range_startk;
309 state->reg = range_to_mtrr(state->reg, state->range_startk,
310 state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
311 state->reg = range_to_mtrr(state->reg, state->hole_startk,
312 state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits);
313 state->range_startk = 0;
314 state->range_sizek = 0;
315 state->hole_startk = 0;
316 state->hole_sizek = 0;
318 /* Allocate an msr */
319 printk_spew(" Allocate an msr - basek = %d, sizek = %d,\n", basek, sizek);
320 state->range_startk = basek;
321 state->range_sizek = sizek;
324 void x86_setup_fixed_mtrrs(void)
326 /* Try this the simple way of incrementally adding together
327 * mtrrs. If this doesn't work out we can get smart again
328 * and clear out the mtrrs.
330 struct var_mtrr_state var_state;
333 /* Initialized the fixed_mtrrs to uncached */
334 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
335 0, NUM_FIXED_RANGES);
336 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
338 /* Now see which of the fixed mtrrs cover ram.
340 search_global_resources(
341 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
342 set_fixed_mtrr_resource, NULL);
343 printk_debug("DONE fixed MTRRs\n");
345 /* enable fixed MTRR */
346 printk_spew("call enable_fixed_mtrr()\n");
350 void x86_setup_var_mtrrs(unsigned address_bits)
351 /* this routine needs to know how many address bits a given processor
352 * supports. CPUs get grumpy when you set too many bits in
353 * their mtrr registers :( I would generically call cpuid here
354 * and find out how many physically supported but some cpus are
355 * buggy, and report more bits then they actually support.
358 /* Try this the simple way of incrementally adding together
359 * mtrrs. If this doesn't work out we can get smart again
360 * and clear out the mtrrs.
362 struct var_mtrr_state var_state;
364 /* Cache as many memory areas as possible */
365 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
366 * In some cases it is definitely possible to do better.
368 var_state.range_startk = 0;
369 var_state.range_sizek = 0;
370 var_state.hole_startk = 0;
371 var_state.hole_sizek = 0;
373 var_state.address_bits = address_bits;
374 search_global_resources(
375 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
376 set_var_mtrr_resource, &var_state);
378 /* Write the last range */
379 var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
380 var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
381 var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
382 var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
383 printk_debug("DONE variable MTRRs\n");
384 printk_debug("Clear out the extra MTRR's\n");
385 /* Clear out the extra MTRR's */
386 while(var_state.reg < MTRRS) {
387 set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
389 printk_spew("call enable_var_mtrr()\n");
391 printk_spew("Leave %s\n", __FUNCTION__);
395 void x86_setup_mtrrs(unsigned address_bits)
397 x86_setup_fixed_mtrrs();
398 x86_setup_var_mtrrs(address_bits);
402 int x86_mtrr_check(void)
404 /* Only Pentium Pro and later have MTRR */
406 printk_debug("\nMTRR check\n");
411 printk_debug("Fixed MTRRs : ");
413 printk_debug("Enabled\n");
415 printk_debug("Disabled\n");
417 printk_debug("Variable MTRRs: ");
419 printk_debug("Enabled\n");
421 printk_debug("Disabled\n");
426 return ((int) msr.lo);