src/cpu/x86/lapic/lapic_cpu_init.c

   1 /*
   2         2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
   3         2005.12 yhlu add _RAMBASE above 1M support for SMP
   4 */
   5
   6 #include <cpu/x86/lapic.h>
   7 #include <delay.h>
   8 #include <string.h>
   9 #include <console/console.h>
  10 #include <arch/hlt.h>
  11 #include <device/device.h>
  12 #include <device/path.h>
  13 #include <smp/atomic.h>
  14 #include <smp/spinlock.h>
  15 #include <cpu/cpu.h>
  16
  17 #if CONFIG_SMP == 1
  18
  19 /* This is a lot more paranoid now, since Linux can NOT handle
  20  * being told there is a CPU when none exists. So any errors
  21  * will return 0, meaning no CPU.
  22  *
  23  * We actually handling that case by noting which cpus startup
  24  * and not telling anyone about the ones that dont.
  25  */
  26 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
  27 {
  28         return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
  29 }
  30
  31 static void copy_secondary_start_to_1m_below(void)
  32 {
  33 #if _RAMBASE >= 0x100000
  34         extern char _secondary_start[];
  35         extern char _secondary_start_end[];
  36         unsigned long code_size;
  37         unsigned long start_eip;
  38
  39         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
  40                 Also We need to copy the _secondary_start to the below 1M region
  41         */
  42         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
  43         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
  44
  45         /* copy the _secondary_start to the ram below 1M*/
  46         memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
  47
  48         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
  49 #endif
  50 }
  51
  52 static int lapic_start_cpu(unsigned long apicid)
  53 {
  54         int timeout;
  55         unsigned long send_status, accept_status, start_eip;
  56         int j, num_starts, maxlvt;
  57         extern char _secondary_start[];
  58
  59         /*
  60          * Starting actual IPI sequence...
  61          */
  62
  63         printk_spew("Asserting INIT.\n");
  64
  65         /*
  66          * Turn INIT on target chip
  67          */
  68         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  69
  70         /*
  71          * Send IPI
  72          */
  73
  74         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  75                                 | LAPIC_DM_INIT);
  76
  77         printk_spew("Waiting for send to finish...\n");
  78         timeout = 0;
  79         do {
  80                 printk_spew("+");
  81                 udelay(100);
  82                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
  83         } while (send_status && (timeout++ < 1000));
  84         if (timeout >= 1000) {
  85                 printk_err("CPU %d: First apic write timed out. Disabling\n",
  86                          apicid);
  87                 // too bad.
  88                 printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  89                 if (lapic_read(LAPIC_ESR)) {
  90                         printk_err("Try to reset ESR\n");
  91                         lapic_write_around(LAPIC_ESR, 0);
  92                         printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  93                 }
  94                 return 0;
  95         }
  96         mdelay(10);
  97
  98         printk_spew("Deasserting INIT.\n");
  99
 100         /* Target chip */
 101         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 102
 103         /* Send IPI */
 104         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 105
 106         printk_spew("Waiting for send to finish...\n");
 107         timeout = 0;
 108         do {
 109                 printk_spew("+");
 110                 udelay(100);
 111                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 112         } while (send_status && (timeout++ < 1000));
 113         if (timeout >= 1000) {
 114                 printk_err("CPU %d: Second apic write timed out. Disabling\n",
 115                          apicid);
 116                 // too bad.
 117                 return 0;
 118         }
 119
 120 #if _RAMBASE >= 0x100000
 121         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 122 #else
 123         start_eip = (unsigned long)_secondary_start;
 124 #endif
 125
 126         printk_debug("start_eip=0x%08lx\n", start_eip);
 127
 128         num_starts = 2;
 129
 130         /*
 131          * Run STARTUP IPI loop.
 132          */
 133         printk_spew("#startup loops: %d.\n", num_starts);
 134
 135         maxlvt = 4;
 136
 137         for (j = 1; j <= num_starts; j++) {
 138                 printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
 139                 lapic_read_around(LAPIC_SPIV);
 140                 lapic_write(LAPIC_ESR, 0);
 141                 lapic_read(LAPIC_ESR);
 142                 printk_spew("After apic_write.\n");
 143
 144                 /*
 145                  * STARTUP IPI
 146                  */
 147
 148                 /* Target chip */
 149                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 150
 151                 /* Boot on the stack */
 152                 /* Kick the second */
 153                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 154                                         | (start_eip >> 12));
 155
 156                 /*
 157                  * Give the other CPU some time to accept the IPI.
 158                  */
 159                 udelay(300);
 160
 161                 printk_spew("Startup point 1.\n");
 162
 163                 printk_spew("Waiting for send to finish...\n");
 164                 timeout = 0;
 165                 do {
 166                         printk_spew("+");
 167                         udelay(100);
 168                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 169                 } while (send_status && (timeout++ < 1000));
 170
 171                 /*
 172                  * Give the other CPU some time to accept the IPI.
 173                  */
 174                 udelay(200);
 175                 /*
 176                  * Due to the Pentium erratum 3AP.
 177                  */
 178                 if (maxlvt > 3) {
 179                         lapic_read_around(LAPIC_SPIV);
 180                         lapic_write(LAPIC_ESR, 0);
 181                 }
 182                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 183                 if (send_status || accept_status)
 184                         break;
 185         }
 186         printk_spew("After Startup.\n");
 187         if (send_status)
 188                 printk_warning("APIC never delivered???\n");
 189         if (accept_status)
 190                 printk_warning("APIC delivery error (%lx).\n", accept_status);
 191         if (send_status || accept_status)
 192                 return 0;
 193         return 1;
 194 }
 195
 196 /* Number of cpus that are currently running in linuxbios */
 197 static atomic_t active_cpus = ATOMIC_INIT(1);
 198
 199 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 200  * Only starting one cpu at a time let's me remove the logic
 201  * for select the stack from assembly language.
 202  *
 203  * In addition communicating by variables to the cpu I
 204  * am starting allows me to veryify it has started before
 205  * start_cpu returns.
 206  */
 207
 208 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 209 static unsigned last_cpu_index = 0;
 210 volatile unsigned long secondary_stack;
 211
 212 int start_cpu(device_t cpu)
 213 {
 214         extern unsigned char _estack[];
 215         struct cpu_info *info;
 216         unsigned long stack_end;
 217         unsigned long apicid;
 218         unsigned long index;
 219         unsigned long count;
 220         int result;
 221
 222         spin_lock(&start_cpu_lock);
 223
 224         /* Get the cpu's apicid */
 225         apicid = cpu->path.u.apic.apic_id;
 226
 227         /* Get an index for the new processor */
 228         index = ++last_cpu_index;
 229
 230         /* Find end of the new processors stack */
 231 #if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
 232         if(index<1) { // only keep bsp on low
 233                 stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 234         } else {
 235                 // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
 236                 stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
 237 #if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10)
 238                 #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n"
 239 #endif
 240                 if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
 241                         printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10);
 242                         die("Can not go on\n");
 243                 }
 244                 stack_end -= sizeof(struct cpu_info);
 245         }
 246 #else
 247         stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 248 #endif
 249
 250
 251         /* Record the index and which cpu structure we are using */
 252         info = (struct cpu_info *)stack_end;
 253         info->index = index;
 254         info->cpu   = cpu;
 255
 256         /* Advertise the new stack to start_cpu */
 257         secondary_stack = stack_end;
 258
 259         /* Until the cpu starts up report the cpu is not enabled */
 260         cpu->enabled = 0;
 261         cpu->initialized = 0;
 262
 263         /* Start the cpu */
 264         result = lapic_start_cpu(apicid);
 265
 266         if (result) {
 267                 result = 0;
 268                 /* Wait 1s or until the new the new cpu calls in */
 269                 for(count = 0; count < 100000 ; count++) {
 270                         if (secondary_stack == 0) {
 271                                 result = 1;
 272                                 break;
 273                         }
 274                         udelay(10);
 275                 }
 276         }
 277         secondary_stack = 0;
 278         spin_unlock(&start_cpu_lock);
 279         return result;
 280 }
 281
 282 /* C entry point of secondary cpus */
 283 void secondary_cpu_init(void)
 284 {
 285         atomic_inc(&active_cpus);
 286 #if SERIAL_CPU_INIT == 1
 287   #if CONFIG_MAX_CPUS>2
 288         spin_lock(&start_cpu_lock);
 289   #endif
 290 #endif
 291         cpu_initialize();
 292 #if SERIAL_CPU_INIT == 1
 293   #if CONFIG_MAX_CPUS>2
 294         spin_unlock(&start_cpu_lock);
 295   #endif
 296 #endif
 297
 298         atomic_dec(&active_cpus);
 299         stop_this_cpu();
 300 }
 301
 302 static void initialize_other_cpus(struct bus *cpu_bus)
 303 {
 304         int old_active_count, active_count;
 305         device_t cpu;
 306         /* Loop through the cpus once getting them started */
 307
 308         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 309                 if (cpu->path.type != DEVICE_PATH_APIC) {
 310                         continue;
 311                 }
 312
 313                 if (!cpu->enabled) {
 314                         continue;
 315                 }
 316
 317                 if (cpu->initialized) {
 318                         continue;
 319                 }
 320
 321                 if (!start_cpu(cpu)) {
 322                         /* Record the error in cpu? */
 323                         printk_err("CPU  %u would not start!\n",
 324                                 cpu->path.u.apic.apic_id);
 325                 }
 326 #if SERIAL_CPU_INIT == 1
 327   #if CONFIG_MAX_CPUS>2
 328                 udelay(10);
 329   #endif
 330 #endif
 331         }
 332
 333         /* Now loop until the other cpus have finished initializing */
 334         old_active_count = 1;
 335         active_count = atomic_read(&active_cpus);
 336         while(active_count > 1) {
 337                 if (active_count != old_active_count) {
 338                         printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
 339                         old_active_count = active_count;
 340                 }
 341                 udelay(10);
 342                 active_count = atomic_read(&active_cpus);
 343         }
 344         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 345                 if (cpu->path.type != DEVICE_PATH_APIC) {
 346                         continue;
 347                 }
 348                 if (!cpu->initialized) {
 349                         printk_err("CPU %u did not initialize!\n",
 350                                 cpu->path.u.apic.apic_id);
 351 #warning "FIXME do I need a mainboard_cpu_fixup function?"
 352                 }
 353         }
 354         printk_debug("All AP CPUs stopped\n");
 355 }
 356
 357 #else /* CONFIG_SMP */
 358 #define initialize_other_cpus(root) do {} while(0)
 359 #endif /* CONFIG_SMP */
 360
 361 void initialize_cpus(struct bus *cpu_bus)
 362 {
 363         struct device_path cpu_path;
 364         struct cpu_info *info;
 365
 366         /* Find the info struct for this cpu */
 367         info = cpu_info();
 368
 369 #if NEED_LAPIC == 1
 370         /* Ensure the local apic is enabled */
 371         enable_lapic();
 372
 373         /* Get the device path of the boot cpu */
 374         cpu_path.type           = DEVICE_PATH_APIC;
 375         cpu_path.u.apic.apic_id = lapicid();
 376 #else
 377         /* Get the device path of the boot cpu */
 378         cpu_path.type           = DEVICE_PATH_CPU;
 379         cpu_path.u.cpu.id       = 0;
 380 #endif
 381
 382         /* Find the device structure for the boot cpu */
 383         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 384
 385 #if CONFIG_SMP == 1
 386         copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 387 #endif
 388
 389         /* Initialize the bootstrap processor */
 390         cpu_initialize();
 391
 392         /* Now initialize the rest of the cpus */
 393         initialize_other_cpus(cpu_bus);
 394 }
 395