src/cpu/x86/lapic/lapic_cpu_init.c

   1 /*
   2         2005.12 yhlu add coreboot_ram cross the vga font buffer handling
   3         2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
   4         2008.05 stepan add support for going back to sipi wait state
   5 */
   6
   7 #include <cpu/x86/lapic.h>
   8 #include <delay.h>
   9 #include <string.h>
  10 #include <console/console.h>
  11 #include <arch/hlt.h>
  12 #include <device/device.h>
  13 #include <device/path.h>
  14 #include <smp/atomic.h>
  15 #include <smp/spinlock.h>
  16 #include <cpu/cpu.h>
  17
  18 #if CONFIG_SMP == 1
  19
  20 #if CONFIG_RAMBASE >= 0x100000
  21 /* This is a lot more paranoid now, since Linux can NOT handle
  22  * being told there is a CPU when none exists. So any errors
  23  * will return 0, meaning no CPU.
  24  *
  25  * We actually handling that case by noting which cpus startup
  26  * and not telling anyone about the ones that dont.
  27  */
  28 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
  29 {
  30         return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
  31 }
  32 #endif
  33
  34 #if CONFIG_HAVE_ACPI_RESUME == 1
  35 char *lowmem_backup;
  36 char *lowmem_backup_ptr;
  37 int  lowmem_backup_size;
  38 #endif
  39
  40 static void copy_secondary_start_to_1m_below(void)
  41 {
  42 #if CONFIG_RAMBASE >= 0x100000
  43         extern char _secondary_start[];
  44         extern char _secondary_start_end[];
  45         unsigned long code_size;
  46         unsigned long start_eip;
  47
  48         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
  49                 Also We need to copy the _secondary_start to the below 1M region
  50         */
  51         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
  52         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
  53
  54 #if CONFIG_HAVE_ACPI_RESUME == 1
  55         /* need to save it for RAM resume */
  56         lowmem_backup_size = code_size;
  57         lowmem_backup = malloc(code_size);
  58         lowmem_backup_ptr = (unsigned char *)start_eip;
  59
  60         if (lowmem_backup == NULL)
  61                 die("Out of backup memory\n");
  62
  63         memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
  64 #endif
  65         /* copy the _secondary_start to the ram below 1M*/
  66         memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
  67
  68         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
  69 #endif
  70 }
  71
  72 static int lapic_start_cpu(unsigned long apicid)
  73 {
  74         int timeout;
  75         unsigned long send_status, accept_status, start_eip;
  76         int j, num_starts, maxlvt;
  77         extern char _secondary_start[];
  78
  79         /*
  80          * Starting actual IPI sequence...
  81          */
  82
  83         printk_spew("Asserting INIT.\n");
  84
  85         /*
  86          * Turn INIT on target chip
  87          */
  88         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  89
  90         /*
  91          * Send IPI
  92          */
  93
  94         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  95                                 | LAPIC_DM_INIT);
  96
  97         printk_spew("Waiting for send to finish...\n");
  98         timeout = 0;
  99         do {
 100                 printk_spew("+");
 101                 udelay(100);
 102                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 103         } while (send_status && (timeout++ < 1000));
 104         if (timeout >= 1000) {
 105                 printk_err("CPU %ld: First apic write timed out. Disabling\n",
 106                          apicid);
 107                 // too bad.
 108                 printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 109                 if (lapic_read(LAPIC_ESR)) {
 110                         printk_err("Try to reset ESR\n");
 111                         lapic_write_around(LAPIC_ESR, 0);
 112                         printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 113                 }
 114                 return 0;
 115         }
 116         mdelay(10);
 117
 118         printk_spew("Deasserting INIT.\n");
 119
 120         /* Target chip */
 121         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 122
 123         /* Send IPI */
 124         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 125
 126         printk_spew("Waiting for send to finish...\n");
 127         timeout = 0;
 128         do {
 129                 printk_spew("+");
 130                 udelay(100);
 131                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 132         } while (send_status && (timeout++ < 1000));
 133         if (timeout >= 1000) {
 134                 printk_err("CPU %ld: Second apic write timed out. Disabling\n",
 135                          apicid);
 136                 // too bad.
 137                 return 0;
 138         }
 139
 140 #if CONFIG_RAMBASE >= 0x100000
 141         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 142 #else
 143         start_eip = (unsigned long)_secondary_start;
 144 #endif
 145
 146         num_starts = 2;
 147
 148         /*
 149          * Run STARTUP IPI loop.
 150          */
 151         printk_spew("#startup loops: %d.\n", num_starts);
 152
 153         maxlvt = 4;
 154
 155         for (j = 1; j <= num_starts; j++) {
 156                 printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid);
 157                 lapic_read_around(LAPIC_SPIV);
 158                 lapic_write(LAPIC_ESR, 0);
 159                 lapic_read(LAPIC_ESR);
 160                 printk_spew("After apic_write.\n");
 161
 162                 /*
 163                  * STARTUP IPI
 164                  */
 165
 166                 /* Target chip */
 167                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 168
 169                 /* Boot on the stack */
 170                 /* Kick the second */
 171                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 172                                         | (start_eip >> 12));
 173
 174                 /*
 175                  * Give the other CPU some time to accept the IPI.
 176                  */
 177                 udelay(300);
 178
 179                 printk_spew("Startup point 1.\n");
 180
 181                 printk_spew("Waiting for send to finish...\n");
 182                 timeout = 0;
 183                 do {
 184                         printk_spew("+");
 185                         udelay(100);
 186                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 187                 } while (send_status && (timeout++ < 1000));
 188
 189                 /*
 190                  * Give the other CPU some time to accept the IPI.
 191                  */
 192                 udelay(200);
 193                 /*
 194                  * Due to the Pentium erratum 3AP.
 195                  */
 196                 if (maxlvt > 3) {
 197                         lapic_read_around(LAPIC_SPIV);
 198                         lapic_write(LAPIC_ESR, 0);
 199                 }
 200                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 201                 if (send_status || accept_status)
 202                         break;
 203         }
 204         printk_spew("After Startup.\n");
 205         if (send_status)
 206                 printk_warning("APIC never delivered???\n");
 207         if (accept_status)
 208                 printk_warning("APIC delivery error (%lx).\n", accept_status);
 209         if (send_status || accept_status)
 210                 return 0;
 211         return 1;
 212 }
 213
 214 /* Number of cpus that are currently running in coreboot */
 215 static atomic_t active_cpus = ATOMIC_INIT(1);
 216
 217 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 218  * Only starting one cpu at a time let's me remove the logic
 219  * for select the stack from assembly language.
 220  *
 221  * In addition communicating by variables to the cpu I
 222  * am starting allows me to veryify it has started before
 223  * start_cpu returns.
 224  */
 225
 226 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 227 static unsigned last_cpu_index = 0;
 228 volatile unsigned long secondary_stack;
 229
 230 int start_cpu(device_t cpu)
 231 {
 232         extern unsigned char _estack[];
 233         struct cpu_info *info;
 234         unsigned long stack_end;
 235         unsigned long apicid;
 236         unsigned long index;
 237         unsigned long count;
 238         int result;
 239
 240         spin_lock(&start_cpu_lock);
 241
 242         /* Get the cpu's apicid */
 243         apicid = cpu->path.apic.apic_id;
 244
 245         /* Get an index for the new processor */
 246         index = ++last_cpu_index;
 247
 248         /* Find end of the new processors stack */
 249 #if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
 250         if(index<1) { // only keep bsp on low
 251                 stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
 252         } else {
 253                 // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
 254                 stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
 255 #if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
 256                 #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
 257 #endif
 258                 if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
 259                         printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
 260                         die("Can not go on\n");
 261                 }
 262                 stack_end -= sizeof(struct cpu_info);
 263         }
 264 #else
 265         stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
 266 #endif
 267
 268
 269         /* Record the index and which cpu structure we are using */
 270         info = (struct cpu_info *)stack_end;
 271         info->index = index;
 272         info->cpu   = cpu;
 273
 274         /* Advertise the new stack to start_cpu */
 275         secondary_stack = stack_end;
 276
 277         /* Until the cpu starts up report the cpu is not enabled */
 278         cpu->enabled = 0;
 279         cpu->initialized = 0;
 280
 281         /* Start the cpu */
 282         result = lapic_start_cpu(apicid);
 283
 284         if (result) {
 285                 result = 0;
 286                 /* Wait 1s or until the new the new cpu calls in */
 287                 for(count = 0; count < 100000 ; count++) {
 288                         if (secondary_stack == 0) {
 289                                 result = 1;
 290                                 break;
 291                         }
 292                         udelay(10);
 293                 }
 294         }
 295         secondary_stack = 0;
 296         spin_unlock(&start_cpu_lock);
 297         return result;
 298 }
 299
 300 #if CONFIG_AP_IN_SIPI_WAIT == 1
 301 /**
 302  * Normally this function is defined in lapic.h as an always inline function
 303  * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
 304  * I think all hyperthreading CPUs might need this version, but I could only
 305  * verify this on the Intel Core Duo
 306  */
 307 void stop_this_cpu(void)
 308 {
 309         int timeout;
 310         unsigned long send_status;
 311         unsigned long id;
 312
 313         id = lapic_read(LAPIC_ID) >> 24;
 314
 315         printk_debug("CPU %ld going down...\n", id);
 316
 317         /* send an LAPIC INIT to myself */
 318         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 319         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
 320
 321         /* wait for the ipi send to finish */
 322 #if 0
 323         // When these two printk_spew calls are not removed, the
 324         // machine will hang when log level is SPEW. Why?
 325         printk_spew("Waiting for send to finish...\n");
 326 #endif
 327         timeout = 0;
 328         do {
 329 #if 0
 330                 printk_spew("+");
 331 #endif
 332                 udelay(100);
 333                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 334         } while (send_status && (timeout++ < 1000));
 335         if (timeout >= 1000) {
 336                 printk_err("timed out\n");
 337         }
 338         mdelay(10);
 339
 340         printk_spew("Deasserting INIT.\n");
 341         /* Deassert the LAPIC INIT */
 342         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 343         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 344
 345         printk_spew("Waiting for send to finish...\n");
 346         timeout = 0;
 347         do {
 348                 printk_spew("+");
 349                 udelay(100);
 350                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 351         } while (send_status && (timeout++ < 1000));
 352         if (timeout >= 1000) {
 353                 printk_err("timed out\n");
 354         }
 355
 356         while(1) {
 357                 hlt();
 358         }
 359 }
 360 #endif
 361
 362 /* C entry point of secondary cpus */
 363 void secondary_cpu_init(void)
 364 {
 365         atomic_inc(&active_cpus);
 366 #if CONFIG_SERIAL_CPU_INIT == 1
 367   #if CONFIG_MAX_CPUS>2
 368         spin_lock(&start_cpu_lock);
 369   #endif
 370 #endif
 371         cpu_initialize();
 372 #if CONFIG_SERIAL_CPU_INIT == 1
 373   #if CONFIG_MAX_CPUS>2
 374         spin_unlock(&start_cpu_lock);
 375   #endif
 376 #endif
 377
 378         atomic_dec(&active_cpus);
 379
 380         stop_this_cpu();
 381 }
 382
 383 static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 384 {
 385         device_t cpu;
 386         /* Loop through the cpus once getting them started */
 387
 388         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 389                 if (cpu->path.type != DEVICE_PATH_APIC) {
 390                         continue;
 391                 }
 392         #if CONFIG_SERIAL_CPU_INIT == 0
 393                 if(cpu==bsp_cpu) {
 394                         continue;
 395                 }
 396         #endif
 397
 398                 if (!cpu->enabled) {
 399                         continue;
 400                 }
 401
 402                 if (cpu->initialized) {
 403                         continue;
 404                 }
 405
 406                 if (!start_cpu(cpu)) {
 407                         /* Record the error in cpu? */
 408                         printk_err("CPU 0x%02x would not start!\n",
 409                                 cpu->path.apic.apic_id);
 410                 }
 411 #if CONFIG_SERIAL_CPU_INIT == 1
 412   #if CONFIG_MAX_CPUS>2
 413                 udelay(10);
 414   #endif
 415 #endif
 416         }
 417
 418 }
 419
 420 static void wait_other_cpus_stop(struct bus *cpu_bus)
 421 {
 422         device_t cpu;
 423         int old_active_count, active_count;
 424         /* Now loop until the other cpus have finished initializing */
 425         old_active_count = 1;
 426         active_count = atomic_read(&active_cpus);
 427         while(active_count > 1) {
 428                 if (active_count != old_active_count) {
 429                         printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
 430                         old_active_count = active_count;
 431                 }
 432                 udelay(10);
 433                 active_count = atomic_read(&active_cpus);
 434         }
 435         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 436                 if (cpu->path.type != DEVICE_PATH_APIC) {
 437                         continue;
 438                 }
 439                 if (!cpu->initialized) {
 440                         printk_err("CPU 0x%02x did not initialize!\n",
 441                                 cpu->path.apic.apic_id);
 442                 }
 443         }
 444         printk_debug("All AP CPUs stopped\n");
 445 }
 446
 447 #else /* CONFIG_SMP */
 448 #define initialize_other_cpus(root) do {} while(0)
 449 #endif /* CONFIG_SMP */
 450
 451 #if CONFIG_WAIT_BEFORE_CPUS_INIT==0
 452         #define cpus_ready_for_init() do {} while(0)
 453 #else
 454         void cpus_ready_for_init(void);
 455 #endif
 456
 457 #if CONFIG_HAVE_SMI_HANDLER
 458 void smm_init(void);
 459 #endif
 460
 461 void initialize_cpus(struct bus *cpu_bus)
 462 {
 463         struct device_path cpu_path;
 464         struct cpu_info *info;
 465
 466         /* Find the info struct for this cpu */
 467         info = cpu_info();
 468
 469 #if NEED_LAPIC == 1
 470         /* Ensure the local apic is enabled */
 471         enable_lapic();
 472
 473         /* Get the device path of the boot cpu */
 474         cpu_path.type           = DEVICE_PATH_APIC;
 475         cpu_path.apic.apic_id = lapicid();
 476 #else
 477         /* Get the device path of the boot cpu */
 478         cpu_path.type           = DEVICE_PATH_CPU;
 479         cpu_path.cpu.id       = 0;
 480 #endif
 481
 482         /* Find the device structure for the boot cpu */
 483         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 484
 485 #if CONFIG_SMP == 1
 486         copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 487 #endif
 488
 489 #if CONFIG_HAVE_SMI_HANDLER
 490         smm_init();
 491 #endif
 492
 493         cpus_ready_for_init();
 494
 495 #if CONFIG_SMP == 1
 496         #if CONFIG_SERIAL_CPU_INIT == 0
 497         /* start all aps at first, so we can init ECC all together */
 498         start_other_cpus(cpu_bus, info->cpu);
 499         #endif
 500 #endif
 501
 502         /* Initialize the bootstrap processor */
 503         cpu_initialize();
 504
 505 #if CONFIG_SMP == 1
 506         #if CONFIG_SERIAL_CPU_INIT == 1
 507         start_other_cpus(cpu_bus, info->cpu);
 508         #endif
 509
 510         /* Now wait the rest of the cpus stop*/
 511         wait_other_cpus_stop(cpu_bus);
 512 #endif
 513 }
 514