2 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
3 2005.12 yhlu add _RAMBASE above 1M support for SMP
4 2008.05 stepan add support for going back to sipi wait state
7 #include <cpu/x86/lapic.h>
10 #include <console/console.h>
12 #include <device/device.h>
13 #include <device/path.h>
14 #include <smp/atomic.h>
15 #include <smp/spinlock.h>
20 #if _RAMBASE >= 0x100000
21 /* This is a lot more paranoid now, since Linux can NOT handle
22 * being told there is a CPU when none exists. So any errors
23 * will return 0, meaning no CPU.
25 * We actually handling that case by noting which cpus startup
26 * and not telling anyone about the ones that dont.
28 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
30 return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
34 static void copy_secondary_start_to_1m_below(void)
36 #if _RAMBASE >= 0x100000
37 extern char _secondary_start[];
38 extern char _secondary_start_end[];
39 unsigned long code_size;
40 unsigned long start_eip;
42 /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
43 Also We need to copy the _secondary_start to the below 1M region
45 start_eip = get_valid_start_eip((unsigned long)_secondary_start);
46 code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
48 /* copy the _secondary_start to the ram below 1M*/
49 memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
51 printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
55 static int lapic_start_cpu(unsigned long apicid)
58 unsigned long send_status, accept_status, start_eip;
59 int j, num_starts, maxlvt;
60 extern char _secondary_start[];
63 * Starting actual IPI sequence...
66 printk_spew("Asserting INIT.\n");
69 * Turn INIT on target chip
71 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
77 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
80 printk_spew("Waiting for send to finish...\n");
85 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
86 } while (send_status && (timeout++ < 1000));
87 if (timeout >= 1000) {
88 printk_err("CPU %d: First apic write timed out. Disabling\n",
91 printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
92 if (lapic_read(LAPIC_ESR)) {
93 printk_err("Try to reset ESR\n");
94 lapic_write_around(LAPIC_ESR, 0);
95 printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
101 printk_spew("Deasserting INIT.\n");
104 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
107 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
109 printk_spew("Waiting for send to finish...\n");
114 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
115 } while (send_status && (timeout++ < 1000));
116 if (timeout >= 1000) {
117 printk_err("CPU %d: Second apic write timed out. Disabling\n",
123 #if _RAMBASE >= 0x100000
124 start_eip = get_valid_start_eip((unsigned long)_secondary_start);
126 start_eip = (unsigned long)_secondary_start;
132 * Run STARTUP IPI loop.
134 printk_spew("#startup loops: %d.\n", num_starts);
138 for (j = 1; j <= num_starts; j++) {
139 printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
140 lapic_read_around(LAPIC_SPIV);
141 lapic_write(LAPIC_ESR, 0);
142 lapic_read(LAPIC_ESR);
143 printk_spew("After apic_write.\n");
150 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
152 /* Boot on the stack */
153 /* Kick the second */
154 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
155 | (start_eip >> 12));
158 * Give the other CPU some time to accept the IPI.
162 printk_spew("Startup point 1.\n");
164 printk_spew("Waiting for send to finish...\n");
169 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
170 } while (send_status && (timeout++ < 1000));
173 * Give the other CPU some time to accept the IPI.
177 * Due to the Pentium erratum 3AP.
180 lapic_read_around(LAPIC_SPIV);
181 lapic_write(LAPIC_ESR, 0);
183 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
184 if (send_status || accept_status)
187 printk_spew("After Startup.\n");
189 printk_warning("APIC never delivered???\n");
191 printk_warning("APIC delivery error (%lx).\n", accept_status);
192 if (send_status || accept_status)
197 /* Number of cpus that are currently running in coreboot */
198 static atomic_t active_cpus = ATOMIC_INIT(1);
200 /* start_cpu_lock covers last_cpu_index and secondary_stack.
201 * Only starting one cpu at a time let's me remove the logic
202 * for select the stack from assembly language.
204 * In addition communicating by variables to the cpu I
205 * am starting allows me to veryify it has started before
209 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
210 static unsigned last_cpu_index = 0;
211 volatile unsigned long secondary_stack;
213 int start_cpu(device_t cpu)
215 extern unsigned char _estack[];
216 struct cpu_info *info;
217 unsigned long stack_end;
218 unsigned long apicid;
223 spin_lock(&start_cpu_lock);
225 /* Get the cpu's apicid */
226 apicid = cpu->path.u.apic.apic_id;
228 /* Get an index for the new processor */
229 index = ++last_cpu_index;
231 /* Find end of the new processors stack */
232 #if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
233 if(index<1) { // only keep bsp on low
234 stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
236 // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
237 stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
238 #if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10)
239 #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n"
241 if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
242 printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10);
243 die("Can not go on\n");
245 stack_end -= sizeof(struct cpu_info);
248 stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
252 /* Record the index and which cpu structure we are using */
253 info = (struct cpu_info *)stack_end;
257 /* Advertise the new stack to start_cpu */
258 secondary_stack = stack_end;
260 /* Until the cpu starts up report the cpu is not enabled */
262 cpu->initialized = 0;
265 result = lapic_start_cpu(apicid);
269 /* Wait 1s or until the new the new cpu calls in */
270 for(count = 0; count < 100000 ; count++) {
271 if (secondary_stack == 0) {
279 spin_unlock(&start_cpu_lock);
283 #if CONFIG_AP_IN_SIPI_WAIT == 1
285 * Normally this function is defined in lapic.h as an always inline function
286 * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
287 * I think all hyperthreading CPUs might need this version, but I could only
288 * verify this on the Intel Core Duo
290 void stop_this_cpu(void)
293 unsigned long send_status;
294 unsigned long lapicid;
296 lapicid = lapic_read(LAPIC_ID) >> 24;
298 printk_debug("CPU %d going down...\n", lapicid);
300 /* send an LAPIC INIT to myself */
301 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));
302 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
304 /* wait for the ipi send to finish */
306 // When these two printk_spew calls are not removed, the
307 // machine will hang when log level is SPEW. Why?
308 printk_spew("Waiting for send to finish...\n");
316 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
317 } while (send_status && (timeout++ < 1000));
318 if (timeout >= 1000) {
319 printk_err("timed out\n");
323 printk_spew("Deasserting INIT.\n");
324 /* Deassert the LAPIC INIT */
325 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid));
326 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
328 printk_spew("Waiting for send to finish...\n");
333 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
334 } while (send_status && (timeout++ < 1000));
335 if (timeout >= 1000) {
336 printk_err("timed out\n");
345 /* C entry point of secondary cpus */
346 void secondary_cpu_init(void)
348 unsigned long cpunum;
350 atomic_inc(&active_cpus);
351 #if SERIAL_CPU_INIT == 1
352 #if CONFIG_MAX_CPUS>2
353 spin_lock(&start_cpu_lock);
357 #if SERIAL_CPU_INIT == 1
358 #if CONFIG_MAX_CPUS>2
359 spin_unlock(&start_cpu_lock);
363 atomic_dec(&active_cpus);
368 static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
371 /* Loop through the cpus once getting them started */
373 for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
374 if (cpu->path.type != DEVICE_PATH_APIC) {
377 #if SERIAL_CPU_INIT == 0
387 if (cpu->initialized) {
391 if (!start_cpu(cpu)) {
392 /* Record the error in cpu? */
393 printk_err("CPU 0x%02x would not start!\n",
394 cpu->path.u.apic.apic_id);
396 #if SERIAL_CPU_INIT == 1
397 #if CONFIG_MAX_CPUS>2
405 static void wait_other_cpus_stop(struct bus *cpu_bus)
408 int old_active_count, active_count;
409 /* Now loop until the other cpus have finished initializing */
410 old_active_count = 1;
411 active_count = atomic_read(&active_cpus);
412 while(active_count > 1) {
413 if (active_count != old_active_count) {
414 printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
415 old_active_count = active_count;
418 active_count = atomic_read(&active_cpus);
420 for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
421 if (cpu->path.type != DEVICE_PATH_APIC) {
424 if (!cpu->initialized) {
425 printk_err("CPU 0x%02x did not initialize!\n",
426 cpu->path.u.apic.apic_id);
429 printk_debug("All AP CPUs stopped\n");
432 #else /* CONFIG_SMP */
433 #define initialize_other_cpus(root) do {} while(0)
434 #endif /* CONFIG_SMP */
436 #if WAIT_BEFORE_CPUS_INIT==0
437 #define cpus_ready_for_init() do {} while(0)
444 void initialize_cpus(struct bus *cpu_bus)
446 struct device_path cpu_path;
447 struct cpu_info *info;
449 /* Find the info struct for this cpu */
453 /* Ensure the local apic is enabled */
456 /* Get the device path of the boot cpu */
457 cpu_path.type = DEVICE_PATH_APIC;
458 cpu_path.u.apic.apic_id = lapicid();
460 /* Get the device path of the boot cpu */
461 cpu_path.type = DEVICE_PATH_CPU;
462 cpu_path.u.cpu.id = 0;
465 /* Find the device structure for the boot cpu */
466 info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
469 copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
476 cpus_ready_for_init();
479 #if SERIAL_CPU_INIT == 0
480 /* start all aps at first, so we can init ECC all together */
481 start_other_cpus(cpu_bus, info->cpu);
485 /* Initialize the bootstrap processor */
489 #if SERIAL_CPU_INIT == 1
490 start_other_cpus(cpu_bus, info->cpu);
493 /* Now wait the rest of the cpus stop*/
494 wait_other_cpus_stop(cpu_bus);