2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2005 Eswar Nallusamy, LANL
6 * Copyright (C) 2005 Tyan
7 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
8 * Copyright (C) 2007 coresystems GmbH
9 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
10 * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
11 * Copyright (C) 2008 VIA Technologies, Inc.
12 * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define CacheSize CONFIG_DCACHE_RAM_SIZE
29 #define CacheBase CONFIG_DCACHE_RAM_BASE
32 #include <cpu/x86/mtrr.h>
34 /* Save the BIST result */
45 /* Set the default memory type and enable fixed and variable MTRRs */
46 movl $MTRRdefType_MSR, %ecx
48 /* Enable Variable and Fixed MTRRs */
49 movl $0x00000c00, %eax
54 movl $fixed_mtrr_msr, %esi
58 jz clear_fixed_var_mtrr_out
64 jmp clear_fixed_var_mtrr
65 clear_fixed_var_mtrr_out:
69 movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
74 /* This assumes we never access addresses above 2^36 in CAR. */
76 movl $(~(CacheSize-1)|0x800),%eax
79 /* enable write base caching so we can do execute in place
85 movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
91 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
95 movl $MTRRdefType_MSR, %ecx
97 /* Enable Variable and Fixed MTRRs */
98 movl $0x00000800, %eax
102 andl $0x9fffffff,%eax
105 /* Read the range with lodsl*/
107 movl $CacheBase, %esi
109 movl $(CacheSize>>2), %ecx
112 movl $CacheBase, %esi
114 movl $(CacheSize>>2), %ecx
116 /* 0x5c5c5c5c is a memory test pattern.
117 * TODO: Check if everything works with the zero pattern as well. */
119 xorl $0x5c5c5c5c,%eax
122 movl CONFIG_XIP_ROM_BASE, %esi
124 movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
127 /* The key point of this CAR code is C7 cache does not turn into
128 * "no fill" mode, which is not compatible with general CAR code.
131 movl $(CacheBase+CacheSize-4), %eax
134 #ifdef CONFIG_CARTEST
135 testok: movb $0x40,%al
154 /* Restore the BIST result */
156 /* We need to set ebp ? No need */
158 pushl %eax /* bist */
160 /* We will not go back */
163 .long 0x250, 0x258, 0x259
164 .long 0x268, 0x269, 0x26A
165 .long 0x26B, 0x26C, 0x26D
168 .long 0x200, 0x201, 0x202, 0x203
169 .long 0x204, 0x205, 0x206, 0x207
170 .long 0x208, 0x209, 0x20A, 0x20B
171 .long 0x20C, 0x20D, 0x20E, 0x20F
172 .long 0x000 /* NULL, end of table */