2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * This source code has been made available to you by IBM on an AS-IS
25 * basis. Anyone receiving this source is licensed under IBM
26 * copyrights to use it in any way he or she deems fit, including
27 * copying it, modifying it, compiling it, and redistributing it either
28 * with or without modifications. No license under IBM patents or
29 * patent applications is to be implied by the copyright license.
31 * Any user of this software should understand that IBM cannot provide
32 * technical support for this software and will not be responsible for
33 * any consequences resulting from the use of this software.
35 * Any person who transfers this source code or any derivative work
36 * must include the IBM copyright notice, this paragraph, and the
37 * preceding two paragraphs in the transferred software.
39 * COPYRIGHT I B M CORPORATION 1995
40 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
45 * Startup Code for IBM 4xx PowerPC based Embedded Boards
47 * Base on the U-Boot Startup Code
49 * The processor starts at 0xfffffffc and the code is executed
52 * The purpose of this code is:
53 * - initalize the processor to a known state
54 * - turn on the I cache so things execute at a reasonable speed
55 * - set up a temporary stack in D cache
63 mtesr r4 /* clear Exception Syndrome Reg */
64 mttcr r4 /* clear Timer Control Reg */
65 mtxer r4 /* clear Fixed-Point Exception Reg */
66 mtevpr r4 /* clear Exception Vector Prefix Reg */
67 li r4,0x1000 /* set ME bit (Machine Exceptions) */
68 oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
69 mtmsr r4 /* change MSR */
70 li r4,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in */
71 /* the dbsr is cleared by setting */
73 mtdbsr r4 /* clear/reset the dbsr */
76 * Invalidate I and D caches. Enable I cache for defined memory
77 * regions to speed things up. Enable D cache for use as
78 * temporary memory until real memory is enabled.
85 * Enable two 128MB cachable instruction regions
87 * 0x00000000 - 0x07FFFFFF
88 * 0xF8000000 - 0xFFFFFFFF
93 mticcr r4 /* instruction cache enable */
97 * Enable dcache region containing CONFIG_DCACHE_RAM_BASE
98 * On reset all regions are set to write-back, so we
99 * just leave them alone.
101 * dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27))
104 lis r4, CONFIG_DCACHE_RAM_BASE@ha
105 ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
110 mtdccr r4 /* data cache enable */