2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config USE_OPTION_TABLE
84 bool "Use CMOS for configuration values"
86 depends on HAVE_OPTION_TABLE
88 Enable this option if coreboot shall read options from the "CMOS"
89 NVRAM instead of using hard coded values.
93 source src/mainboard/Kconfig
94 source src/arch/i386/Kconfig
99 source src/cpu/Kconfig
100 comment "Northbridge"
101 source src/northbridge/Kconfig
102 comment "Southbridge"
103 source src/southbridge/Kconfig
105 source src/superio/Kconfig
107 source src/devices/Kconfig
111 menu "Generic Drivers"
112 source src/drivers/Kconfig
115 config PCI_BUS_SEGN_BITS
119 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
123 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
147 config MMCONF_SUPPORT_DEFAULT
151 config MMCONF_SUPPORT
158 source src/console/Kconfig
160 config HAVE_ACPI_RESUME
164 config HAVE_ACPI_SLIC
168 config ACPI_SSDTX_NUM
172 config HAVE_HARD_RESET
174 default y if BOARD_HAS_HARD_RESET
177 This variable specifies whether a given board has a hard_reset
178 function, no matter if it's provided by board code or chipset code.
180 config HAVE_INIT_TIMER
182 default n if UDELAY_IO
185 config HAVE_MAINBOARD_RESOURCES
189 config USE_OPTION_TABLE
193 config HAVE_OPTION_TABLE
197 This variable specifies whether a given board has a cmos.layout
198 file containing NVRAM/CMOS bit definitions.
199 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
205 config HAVE_SMI_HANDLER
209 config PCI_IO_CFG_EXT
217 # TODO: Can probably be removed once all chipsets have kconfig options for it.
222 config USE_WATCHDOG_ON_BOOT
230 Build board-specific VGA code.
236 Enable Unified Memory Architecture for graphics.
243 #TODO Remove this option or make it useful.
244 config HAVE_LOW_TABLES
248 This Option is unused in the code. Since two boards try to set it to
249 'n', they may be broken. We either need to make the option useful or
250 get rid of it. The broken boards are:
254 config HAVE_HIGH_TABLES
258 This variable specifies whether a given northbridge has high table
260 It is set in northbridge/*/Kconfig.
261 Whether or not the high tables are actually written by coreboot is
262 configurable by the user via WRITE_HIGH_TABLES.
264 config HAVE_ACPI_TABLES
267 This variable specifies whether a given board has ACPI table support.
268 It is usually set in mainboard/*/Kconfig.
269 Whether or not the ACPI tables are actually generated by coreboot
270 is configurable by the user via GENERATE_ACPI_TABLES.
275 This variable specifies whether a given board has MP table support.
276 It is usually set in mainboard/*/Kconfig.
277 Whether or not the MP table is actually generated by coreboot
278 is configurable by the user via GENERATE_MP_TABLE.
280 config HAVE_PIRQ_TABLE
283 This variable specifies whether a given board has PIRQ table support.
284 It is usually set in mainboard/*/Kconfig.
285 Whether or not the PIRQ table is actually generated by coreboot
286 is configurable by the user via GENERATE_PIRQ_TABLE.
288 #These Options are here to avoid "undefined" warnings.
289 #The actual selection and help texts are in the following menu.
291 config GENERATE_ACPI_TABLES
293 default HAVE_ACPI_TABLES
295 config GENERATE_MP_TABLE
297 default HAVE_MP_TABLE
299 config GENERATE_PIRQ_TABLE
301 default HAVE_PIRQ_TABLE
303 config WRITE_HIGH_TABLES
305 default HAVE_HIGH_TABLES
309 config WRITE_HIGH_TABLES
310 bool "Write 'high' tables to avoid being overwritten in F segment"
311 depends on HAVE_HIGH_TABLES
315 bool "Generate Multiboot tables (for GRUB2)"
318 config GENERATE_ACPI_TABLES
319 depends on HAVE_ACPI_TABLES
320 bool "Generate ACPI tables"
323 Generate ACPI tables for this board.
327 config GENERATE_MP_TABLE
328 depends on HAVE_MP_TABLE
329 bool "Generate an MP table"
332 Generate an MP table (conforming to the Intel MultiProcessor
333 specification 1.4) for this board.
337 config GENERATE_PIRQ_TABLE
338 depends on HAVE_PIRQ_TABLE
339 bool "Generate a PIRQ table"
342 Generate a PIRQ table for this board.
351 prompt "Add a payload"
357 Select this option if you want to create an "empty" coreboot
358 ROM image for a certain mainboard, i.e. a coreboot ROM image
359 which does not yet contain a payload.
361 For such an image to be useful, you have to use 'cbfstool'
362 to add a payload to the ROM image later.
365 bool "An ELF executable payload"
367 Select this option if you have a payload image (an ELF file)
368 which coreboot should run as soon as the basic hardware
369 initialization is completed.
371 You will be able to specify the location and file name of the
376 config FALLBACK_PAYLOAD_FILE
377 string "Payload path and filename"
378 depends on PAYLOAD_ELF
379 default "payload.elf"
381 The path and filename of the ELF executable file to use as payload.
383 # TODO: Defined if no payload? Breaks build?
384 config COMPRESSED_PAYLOAD_LZMA
385 bool "Use LZMA compression for payloads"
387 depends on PAYLOAD_ELF
389 In order to reduce the size payloads take up in the ROM chip
390 coreboot can compress them using the LZMA algorithm.
392 config COMPRESSED_PAYLOAD_NRV2B
401 bool "Add a VGA BIOS image"
403 Select this option if you have a VGA BIOS image that you would
404 like to add to your ROM.
406 You will be able to specify the location and file name of the
409 config FALLBACK_VGA_BIOS_FILE
410 string "VGA BIOS path and filename"
412 default "vgabios.bin"
414 The path and filename of the file to use as VGA BIOS.
416 config FALLBACK_VGA_BIOS_ID
417 string "VGA device PCI IDs"
421 The comma-separated PCI vendor and device ID that would associate
422 your VGA BIOS to your video card.
426 In the above example 1106 is the PCI vendor ID (in hex, but without
427 the "0x" prefix) and 3230 specifies the PCI device ID of the
428 video card (also in hex, without "0x" prefix).
431 bool "Add an MBI image"
432 depends on NORTHBRIDGE_INTEL_I82830
434 Select this option if you have an Intel MBI image that you would
435 like to add to your ROM.
437 You will be able to specify the location and file name of the
440 config FALLBACK_MBI_FILE
441 string "Intel MBI path and filename"
445 The path and filename of the file to use as VGA BIOS.
450 depends on PCI_OPTION_ROM_RUN_YABEL
453 prompt "Show graphical bootsplash"
455 depends on PCI_OPTION_ROM_RUN_YABEL
457 This option shows a graphical bootsplash screen. The grapics are
458 loaded from the CBFS file bootsplash.jpg.
460 config FALLBACK_BOOTSPLASH_FILE
461 string "Bootsplash path and filename"
462 depends on BOOTSPLASH
463 default "bootsplash.jpg"
465 The path and filename of the file to use as graphical bootsplash
466 screen. The file format has to be jpg.
468 # TODO: Turn this into a "choice".
469 config FRAMEBUFFER_VESA_MODE
470 prompt "VESA framebuffer video mode"
473 depends on BOOTSPLASH
475 This option sets the resolution used for the coreboot framebuffer and
476 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
477 some day make this a "choice".
479 config COREBOOT_KEEP_FRAMEBUFFER
480 prompt "Keep VESA framebuffer"
482 depends on BOOTSPLASH
484 This option keeps the framebuffer mode set after coreboot finishes
485 execution. If this option is enabled, coreboot will pass a
486 framebuffer entry in its coreboot table and the payload will need a
487 framebuffer driver. If this option is disabled, coreboot will switch
488 back to text mode before handing control to a payload.
494 # TODO: Better help text and detailed instructions.
496 bool "GDB debugging support"
499 If enabled, you will be able to set breakpoints for gdb debugging.
500 See src/arch/i386/lib/c_start.S for details.
502 config DEBUG_RAM_SETUP
503 bool "Output verbose RAM init debug messages"
505 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
506 || NORTHBRIDGE_AMD_AMDK8 \
507 || NORTHBRIDGE_VIA_CN700 \
508 || NORTHBRIDGE_VIA_CX700 \
509 || NORTHBRIDGE_VIA_VX800 \
510 || NORTHBRIDGE_INTEL_E7501 \
511 || NORTHBRIDGE_INTEL_I440BX \
512 || NORTHBRIDGE_INTEL_I82810 \
513 || NORTHBRIDGE_INTEL_I82830 \
514 || NORTHBRIDGE_INTEL_I945)
516 This option enables additional RAM init related debug messages.
517 It is recommended to enable this when debugging issues on your
518 board which might be RAM init related.
520 Note: This option will increase the size of the coreboot image.
525 bool "Check PIRQ table consistency"
527 depends on GENERATE_PIRQ_TABLE
532 bool "Output verbose SMBus debug messages"
534 depends on (SOUTHBRIDGE_VIA_VT8237R \
535 || NORTHBRIDGE_VIA_VX800 \
536 || NORTHBRIDGE_VIA_CX700 \
537 || NORTHBRIDGE_AMD_AMDK8 \
538 || NORTHBRIDGE_AMD_AMDFAM10 \
539 || BOARD_LIPPERT_SPACERUNNER_LX \
540 || SOUTHBRIDGE_VIA_VT8231)
542 This option enables additional SMBus (and SPD) debug messages.
544 Note: This option will increase the size of the coreboot image.
549 bool "Output verbose SMI debug messages"
551 depends on HAVE_SMI_HANDLER
553 This option enables additional SMI related debug messages.
555 Note: This option will increase the size of the coreboot image.
559 config DEBUG_SMM_RELOCATION
560 bool "Debug SMM relocation code"
562 depends on HAVE_SMI_HANDLER
564 This option enables additional SMM handler relocation related
567 Note: This option will increase the size of the coreboot image.
572 bool "Output verbose x86emu debug messages"
574 depends on PCI_OPTION_ROM_RUN_YABEL
576 This option enables additional x86emu related debug messages.
578 Note: This option will increase the size of the coreboot image.
582 config X86EMU_DEBUG_JMP
583 bool "Trace JMP/RETF"
585 depends on X86EMU_DEBUG
587 Print information about JMP and RETF opcodes from x86emu.
589 Note: This option will increase the size of the coreboot image.
593 config X86EMU_DEBUG_TRACE
594 bool "Trace all opcodes"
596 depends on X86EMU_DEBUG
598 Print _all_ opcodes that are executed by x86emu.
600 WARNING: This will produce a LOT of output and take a long time.
602 Note: This option will increase the size of the coreboot image.
606 config X86EMU_DEBUG_PNP
607 bool "Log Plug&Play accesses"
609 depends on X86EMU_DEBUG
611 Print Plug And Play accesses made by option ROMs.
613 Note: This option will increase the size of the coreboot image.
617 config X86EMU_DEBUG_DISK
620 depends on X86EMU_DEBUG
622 Print Disk I/O related messages.
624 Note: This option will increase the size of the coreboot image.
628 config X86EMU_DEBUG_PMM
631 depends on X86EMU_DEBUG
633 Print messages related to POST Memory Manager (PMM).
635 Note: This option will increase the size of the coreboot image.
640 config X86EMU_DEBUG_VBE
641 bool "Debug VESA BIOS Extensions"
643 depends on X86EMU_DEBUG
645 Print messages related to VESA BIOS Extension (VBE) functions.
647 Note: This option will increase the size of the coreboot image.
651 config X86EMU_DEBUG_INT10
652 bool "Redirect INT10 output to console"
654 depends on X86EMU_DEBUG
656 Let INT10 (i.e. character output) calls print messages to debug output.
658 Note: This option will increase the size of the coreboot image.
662 config X86EMU_DEBUG_INTERRUPTS
663 bool "Log intXX calls"
665 depends on X86EMU_DEBUG
667 Print messages related to interrupt handling.
669 Note: This option will increase the size of the coreboot image.
673 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
674 bool "Log special memory accesses"
676 depends on X86EMU_DEBUG
678 Print messages related to accesses to certain areas of the virtual
679 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
681 Note: This option will increase the size of the coreboot image.
685 config X86EMU_DEBUG_MEM
686 bool "Log all memory accesses"
688 depends on X86EMU_DEBUG
690 Print memory accesses made by option ROM.
691 Note: This also includes accesses to fetch instructions.
693 Note: This option will increase the size of the coreboot image.
697 config X86EMU_DEBUG_IO
698 bool "Log IO accesses"
700 depends on X86EMU_DEBUG
702 Print I/O accesses made by option ROM.
704 Note: This option will increase the size of the coreboot image.
709 bool "Built-in low-level shell"
712 If enabled, you will have a low level shell to examine your machine.
713 Put llshell() in your (romstage) code to start the shell.
714 See src/arch/i386/llshell/llshell.inc for details.
718 config LIFT_BSP_APIC_ID
722 # These probably belong somewhere else, but they are needed somewhere.
723 config AP_CODE_IN_CAR
727 config ENABLE_APIC_EXT_ID
731 config WARNINGS_ARE_ERRORS
735 config ID_SECTION_OFFSET
739 source src/Kconfig.deprecated_options