2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
78 source src/mainboard/Kconfig
79 source src/arch/i386/Kconfig
84 source src/cpu/Kconfig
87 menu "HyperTransport setup"
88 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
91 prompt "HyperTransport frequency"
92 default LIMIT_HT_SPEED_AUTO
94 This option sets the maximum permissible HyperTransport link
97 Use of this option will only limit the autodetected HT frequency.
98 It will not (and cannot) increase the frequency beyond the
101 This is primarily used to work around poorly designed or laid out
102 HT traces on certain motherboards.
104 config LIMIT_HT_SPEED_200
105 bool "Limit HT frequency to 200MHz"
106 config LIMIT_HT_SPEED_400
107 bool "Limit HT frequency to 400MHz"
108 config LIMIT_HT_SPEED_600
109 bool "Limit HT frequency to 600MHz"
110 config LIMIT_HT_SPEED_800
111 bool "Limit HT frequency to 800MHz"
112 config LIMIT_HT_SPEED_1000
113 bool "Limit HT frequency to 1.0GHz"
114 config LIMIT_HT_SPEED_1200
115 bool "Limit HT frequency to 1.2GHz"
116 config LIMIT_HT_SPEED_1400
117 bool "Limit HT frequency to 1.4GHz"
118 config LIMIT_HT_SPEED_1600
119 bool "Limit HT frequency to 1.6GHz"
120 config LIMIT_HT_SPEED_1800
121 bool "Limit HT frequency to 1.8GHz"
122 config LIMIT_HT_SPEED_2000
123 bool "Limit HT frequency to 2.0GHz"
124 config LIMIT_HT_SPEED_2200
125 bool "Limit HT frequency to 2.2GHz"
126 config LIMIT_HT_SPEED_2400
127 bool "Limit HT frequency to 2.4GHz"
128 config LIMIT_HT_SPEED_2600
129 bool "Limit HT frequency to 2.6GHz"
130 config LIMIT_HT_SPEED_AUTO
131 bool "Autodetect HT frequency"
135 prompt "HyperTransport downlink width"
136 default LIMIT_HT_DOWN_WIDTH_16
138 This option sets the maximum permissible HyperTransport
141 Use of this option will only limit the autodetected HT width.
142 It will not (and cannot) increase the width beyond the autodetected
145 This is primarily used to work around poorly designed or laid out HT
146 traces on certain motherboards.
148 config LIMIT_HT_DOWN_WIDTH_8
150 config LIMIT_HT_DOWN_WIDTH_16
155 prompt "HyperTransport uplink width"
156 default LIMIT_HT_UP_WIDTH_16
158 This option sets the maximum permissible HyperTransport
161 Use of this option will only limit the autodetected HT width.
162 It will not (and cannot) increase the width beyond the autodetected
165 This is primarily used to work around poorly designed or laid out HT
166 traces on certain motherboards.
168 config LIMIT_HT_UP_WIDTH_8
170 config LIMIT_HT_UP_WIDTH_16
176 source src/northbridge/Kconfig
177 comment "Southbridge"
178 source src/southbridge/Kconfig
180 source src/superio/Kconfig
182 source src/devices/Kconfig
186 config PCI_BUS_SEGN_BITS
190 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
194 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
210 config LB_CKS_RANGE_START
214 config LB_CKS_RANGE_END
238 config USE_PRINTK_IN_CAR
242 config USE_OPTION_TABLE
250 config MMCONF_SUPPORT_DEFAULT
254 config MMCONF_SUPPORT
265 source src/console/Kconfig
267 config HAVE_ACPI_RESUME
271 config ACPI_SSDTX_NUM
275 config HAVE_HARD_RESET
277 default y if BOARD_HAS_HARD_RESET
280 This variable specifies whether a given board has a hard_reset
281 function, no matter if it's provided by board code or chipset code.
283 config HAVE_INIT_TIMER
285 default n if UDELAY_IO
288 config HAVE_MAINBOARD_RESOURCES
292 config HAVE_OPTION_TABLE
296 This variable specifies whether a given board has a cmos.layout
297 file containing NVRAM/CMOS bit definitions.
298 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
304 config HAVE_SMI_HANDLER
308 config PCI_IO_CFG_EXT
316 # TODO: Can probably be removed once all chipsets have kconfig options for it.
321 config USE_WATCHDOG_ON_BOOT
329 Build board-specific VGA code.
335 Enable Unified Memory Architecture for graphics.
342 #TODO Remove this option or make it useful.
343 config HAVE_LOW_TABLES
347 This Option is unused in the code. Since two boards try to set it to
348 'n', they may be broken. We either need to make the option useful or
349 get rid of it. The broken boards are:
353 config HAVE_HIGH_TABLES
357 This variable specifies whether a given northbridge has high table
359 It is set in northbridge/*/Kconfig.
360 Whether or not the high tables are actually written by coreboot is
361 configurable by the user via WRITE_HIGH_TABLES.
363 config HAVE_ACPI_TABLES
366 This variable specifies whether a given board has ACPI table support.
367 It is usually set in mainboard/*/Kconfig.
368 Whether or not the ACPI tables are actually generated by coreboot
369 is configurable by the user via GENERATE_ACPI_TABLES.
374 This variable specifies whether a given board has MP table support.
375 It is usually set in mainboard/*/Kconfig.
376 Whether or not the MP table is actually generated by coreboot
377 is configurable by the user via GENERATE_MP_TABLE.
379 config HAVE_PIRQ_TABLE
382 This variable specifies whether a given board has PIRQ table support.
383 It is usually set in mainboard/*/Kconfig.
384 Whether or not the PIRQ table is actually generated by coreboot
385 is configurable by the user via GENERATE_PIRQ_TABLE.
387 #These Options are here to avoid "undefined" warnings.
388 #The actual selection and help texts are in the following menu.
390 config GENERATE_ACPI_TABLES
392 default HAVE_ACPI_TABLES
394 config GENERATE_MP_TABLE
396 default HAVE_MP_TABLE
398 config GENERATE_PIRQ_TABLE
400 default HAVE_PIRQ_TABLE
402 config WRITE_HIGH_TABLES
404 default HAVE_HIGH_TABLES
408 config WRITE_HIGH_TABLES
409 bool "Write 'high' tables to avoid being overwritten in F segment"
410 depends on HAVE_HIGH_TABLES
414 bool "Generate Multiboot tables (for GRUB2)"
417 config GENERATE_ACPI_TABLES
418 depends on HAVE_ACPI_TABLES
419 bool "Generate ACPI tables"
422 Generate ACPI tables for this board.
426 config GENERATE_MP_TABLE
427 depends on HAVE_MP_TABLE
428 bool "Generate an MP table"
431 Generate an MP table (conforming to the Intel MultiProcessor
432 specification 1.4) for this board.
436 config GENERATE_PIRQ_TABLE
437 depends on HAVE_PIRQ_TABLE
438 bool "Generate a PIRQ table"
441 Generate a PIRQ table for this board.
450 prompt "Add a payload"
456 Select this option if you want to create an "empty" coreboot
457 ROM image for a certain mainboard, i.e. a coreboot ROM image
458 which does not yet contain a payload.
460 For such an image to be useful, you have to use 'cbfstool'
461 to add a payload to the ROM image later.
464 bool "An ELF executable payload"
466 Select this option if you have a payload image (an ELF file)
467 which coreboot should run as soon as the basic hardware
468 initialization is completed.
470 You will be able to specify the location and file name of the
475 config FALLBACK_PAYLOAD_FILE
476 string "Payload path and filename"
477 depends on PAYLOAD_ELF
478 default "payload.elf"
480 The path and filename of the ELF executable file to use as payload.
482 # TODO: Defined if no payload? Breaks build?
483 config COMPRESSED_PAYLOAD_LZMA
484 bool "Use LZMA compression for payloads"
486 depends on PAYLOAD_ELF
488 In order to reduce the size payloads take up in the ROM chip
489 coreboot can compress them using the LZMA algorithm.
491 config COMPRESSED_PAYLOAD_NRV2B
500 bool "Add a VGA BIOS image"
502 Select this option if you have a VGA BIOS image that you would
503 like to add to your ROM.
505 You will be able to specify the location and file name of the
508 config FALLBACK_VGA_BIOS_FILE
509 string "VGA BIOS path and filename"
511 default "vgabios.bin"
513 The path and filename of the file to use as VGA BIOS.
515 config FALLBACK_VGA_BIOS_ID
516 string "VGA device PCI IDs"
520 The comma-separated PCI vendor and device ID that would associate
521 your VGA BIOS to your video card.
525 In the above example 1106 is the PCI vendor ID (in hex, but without
526 the "0x" prefix) and 3230 specifies the PCI device ID of the
527 video card (also in hex, without "0x" prefix).
530 bool "Add an MBI image"
531 depends on NORTHBRIDGE_INTEL_I82830
533 Select this option if you have an Intel MBI image that you would
534 like to add to your ROM.
536 You will be able to specify the location and file name of the
539 config FALLBACK_MBI_FILE
540 string "Intel MBI path and filename"
544 The path and filename of the file to use as VGA BIOS.
549 depends on PCI_OPTION_ROM_RUN_YABEL
552 prompt "Show graphical bootsplash"
554 depends on PCI_OPTION_ROM_RUN_YABEL
556 This option shows a graphical bootsplash screen. The grapics are
557 loaded from the CBFS file bootsplash.jpg.
559 config FALLBACK_BOOTSPLASH_FILE
560 string "Bootsplash path and filename"
561 depends on BOOTSPLASH
562 default "bootsplash.jpg"
564 The path and filename of the file to use as graphical bootsplash
565 screen. The file format has to be jpg.
567 # TODO: Turn this into a "choice".
568 config FRAMEBUFFER_VESA_MODE
569 prompt "VESA framebuffer video mode"
572 depends on BOOTSPLASH
574 This option sets the resolution used for the coreboot framebuffer and
575 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
576 some day make this a "choice".
578 config COREBOOT_KEEP_FRAMEBUFFER
579 prompt "Keep VESA framebuffer"
581 depends on BOOTSPLASH
583 This option keeps the framebuffer mode set after coreboot finishes
584 execution. If this option is enabled, coreboot will pass a
585 framebuffer entry in its coreboot table and the payload will need a
586 framebuffer driver. If this option is disabled, coreboot will switch
587 back to text mode before handing control to a payload.
593 # TODO: Better help text and detailed instructions.
595 bool "GDB debugging support"
598 If enabled, you will be able to set breakpoints for gdb debugging.
599 See src/arch/i386/lib/c_start.S for details.
601 config DEBUG_RAM_SETUP
602 bool "Output verbose RAM init debug messages"
604 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
605 || NORTHBRIDGE_AMD_AMDK8 \
606 || NORTHBRIDGE_VIA_CN700 \
607 || NORTHBRIDGE_VIA_CX700 \
608 || NORTHBRIDGE_VIA_VX800 \
609 || NORTHBRIDGE_INTEL_E7501 \
610 || NORTHBRIDGE_INTEL_I440BX \
611 || NORTHBRIDGE_INTEL_I82810 \
612 || NORTHBRIDGE_INTEL_I82830 \
613 || NORTHBRIDGE_INTEL_I945)
615 This option enables additional RAM init related debug messages.
616 It is recommended to enable this when debugging issues on your
617 board which might be RAM init related.
619 Note: This option will increase the size of the coreboot image.
624 bool "Output verbose SMBus debug messages"
626 depends on (SOUTHBRIDGE_VIA_VT8237R \
627 || NORTHBRIDGE_VIA_VX800 \
628 || NORTHBRIDGE_VIA_CX700 \
629 || NORTHBRIDGE_AMD_AMDK8)
631 This option enables additional SMBus (and SPD) debug messages.
633 Note: This option will increase the size of the coreboot image.
638 bool "Output verbose SMI debug messages"
640 depends on HAVE_SMI_HANDLER
642 This option enables additional SMI related debug messages.
644 Note: This option will increase the size of the coreboot image.
649 bool "Output verbose x86emu debug messages"
651 depends on PCI_OPTION_ROM_RUN_YABEL
653 This option enables additional x86emu related debug messages.
655 Note: This option will increase the size of the coreboot image.
659 config X86EMU_DEBUG_JMP
660 bool "Trace JMP/RETF"
662 depends on X86EMU_DEBUG
664 Print information about JMP and RETF opcodes from x86emu.
666 Note: This option will increase the size of the coreboot image.
670 config X86EMU_DEBUG_TRACE
671 bool "Trace all opcodes"
673 depends on X86EMU_DEBUG
675 Print _all_ opcodes that are executed by x86emu.
677 WARNING: This will produce a LOT of output and take a long time.
679 Note: This option will increase the size of the coreboot image.
683 config X86EMU_DEBUG_PNP
684 bool "Log Plug&Play accesses"
686 depends on X86EMU_DEBUG
688 Print Plug And Play accesses made by option ROMs.
690 Note: This option will increase the size of the coreboot image.
694 config X86EMU_DEBUG_DISK
697 depends on X86EMU_DEBUG
699 Print Disk I/O related messages.
701 Note: This option will increase the size of the coreboot image.
705 config X86EMU_DEBUG_PMM
708 depends on X86EMU_DEBUG
710 Print messages related to POST Memory Manager (PMM).
712 Note: This option will increase the size of the coreboot image.
717 config X86EMU_DEBUG_VBE
718 bool "Debug VESA BIOS Extensions"
720 depends on X86EMU_DEBUG
722 Print messages related to VESA BIOS Extension (VBE) functions.
724 Note: This option will increase the size of the coreboot image.
728 config X86EMU_DEBUG_INT10
729 bool "Redirect INT10 output to console"
731 depends on X86EMU_DEBUG
733 Let INT10 (i.e. character output) calls print messages to debug output.
735 Note: This option will increase the size of the coreboot image.
739 config X86EMU_DEBUG_INTERRUPTS
740 bool "Log intXX calls"
742 depends on X86EMU_DEBUG
744 Print messages related to interrupt handling.
746 Note: This option will increase the size of the coreboot image.
750 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
751 bool "Log special memory accesses"
753 depends on X86EMU_DEBUG
755 Print messages related to accesses to certain areas of the virtual
756 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
758 Note: This option will increase the size of the coreboot image.
762 config X86EMU_DEBUG_MEM
763 bool "Log all memory accesses"
765 depends on X86EMU_DEBUG
767 Print memory accesses made by option ROM.
768 Note: This also includes accesses to fetch instructions.
770 Note: This option will increase the size of the coreboot image.
774 config X86EMU_DEBUG_IO
775 bool "Log IO accesses"
777 depends on X86EMU_DEBUG
779 Print I/O accesses made by option ROM.
781 Note: This option will increase the size of the coreboot image.
786 bool "Built-in low-level shell"
789 If enabled, you will have a low level shell to examine your machine.
790 Put llshell() in your (romstage) code to start the shell.
791 See src/arch/i386/llshell/llshell.inc for details.
795 config LIFT_BSP_APIC_ID
799 # These probably belong somewhere else, but they are needed somewhere.
800 config AP_CODE_IN_CAR
808 config ENABLE_APIC_EXT_ID
812 config WARNINGS_ARE_ERRORS
816 config ID_SECTION_OFFSET
820 source src/Kconfig.deprecated_options