2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
51 source src/mainboard/Kconfig
52 source src/arch/i386/Kconfig
57 source src/cpu/Kconfig
60 menu "HyperTransport Setup"
61 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
64 prompt "HyperTransport Frequency"
65 default LIMIT_HT_SPEED_AUTO
67 This option sets the maximum permissible HyperTransport link frequency.
68 Use of this option will only limit the autodetected HT frequency; it will not (and cannot) increase the frequency beyond the autodetected limits.
69 This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
71 config LIMIT_HT_SPEED_200
72 bool "Limit HT frequency to 200MHz"
73 config LIMIT_HT_SPEED_400
74 bool "Limit HT frequency to 400MHz"
75 config LIMIT_HT_SPEED_600
76 bool "Limit HT frequency to 600MHz"
77 config LIMIT_HT_SPEED_800
78 bool "Limit HT frequency to 800MHz"
79 config LIMIT_HT_SPEED_1000
80 bool "Limit HT frequency to 1.0GHz"
81 config LIMIT_HT_SPEED_1200
82 bool "Limit HT frequency to 1.2GHz"
83 config LIMIT_HT_SPEED_1400
84 bool "Limit HT frequency to 1.4GHz"
85 config LIMIT_HT_SPEED_1600
86 bool "Limit HT frequency to 1.6GHz"
87 config LIMIT_HT_SPEED_1800
88 bool "Limit HT frequency to 1.6GHz"
89 config LIMIT_HT_SPEED_2000
90 bool "Limit HT frequency to 2.0GHz"
91 config LIMIT_HT_SPEED_2200
92 bool "Limit HT frequency to 2.2GHz"
93 config LIMIT_HT_SPEED_2400
94 bool "Limit HT frequency to 2.4GHz"
95 config LIMIT_HT_SPEED_2600
96 bool "Limit HT frequency to 2.6GHz"
97 config LIMIT_HT_SPEED_AUTO
98 bool "Autodetect HT frequency"
102 prompt "HyperTransport Downlink Width"
103 default LIMIT_HT_DOWN_WIDTH_16
105 This option sets the maximum permissible HyperTransport link width.
106 Use of this option will only limit the autodetected HT width; it will not (and cannot) increase the width beyond the autodetected limits.
107 This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
109 config LIMIT_HT_DOWN_WIDTH_8
111 config LIMIT_HT_DOWN_WIDTH_16
116 prompt "HyperTransport Uplink Width"
117 default LIMIT_HT_UP_WIDTH_16
119 This option sets the maximum permissible HyperTransport link width.
120 Use of this option will only limit the autodetected HT width; it will not (and cannot) increase the width beyond the autodetected limits.
121 This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
123 config LIMIT_HT_UP_WIDTH_8
125 config LIMIT_HT_UP_WIDTH_16
131 source src/northbridge/Kconfig
132 comment "Southbridge"
133 source src/southbridge/Kconfig
135 source src/superio/Kconfig
137 source src/devices/Kconfig
141 config PCI_BUS_SEGN_BITS
145 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
149 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
165 config LB_CKS_RANGE_START
169 config LB_CKS_RANGE_END
193 config USE_PRINTK_IN_CAR
197 config USE_OPTION_TABLE
205 config MMCONF_SUPPORT_DEFAULT
209 config MMCONF_SUPPORT
220 source src/console/Kconfig
222 config HAVE_ACPI_RESUME
226 config ACPI_SSDTX_NUM
230 config HAVE_FALLBACK_BOOT
234 config USE_FALLBACK_IMAGE
238 config HAVE_FAILOVER_BOOT
242 config USE_FAILOVER_IMAGE
246 config HAVE_HARD_RESET
248 default y if BOARD_HAS_HARD_RESET
251 This variable specifies whether a given board has a hard_reset
252 function, no matter if it's provided by board code or chipset code.
254 config BOARD_HAS_HARD_RESET
258 This variable specifies whether a given board has a reset.c
259 file containing a hard_reset() function.
261 config BOARD_HAS_FADT
265 This variable specifies whether a given board has a board-local
266 FADT in fadt.c. Long-term, those should be moved to appropriate
267 chipset components (eg. southbridge)
269 config HAVE_BUS_CONFIG
273 This variable specifies whether a given board has a get_bus_conf.c
274 file containing bus configuration data.
276 config HAVE_INIT_TIMER
278 default n if UDELAY_IO
281 config HAVE_MAINBOARD_RESOURCES
285 config HAVE_OPTION_TABLE
289 This variable specifies whether a given board has a cmos.layout
290 file containing NVRAM/CMOS bit definitions.
291 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
297 config HAVE_SMI_HANDLER
301 config PCI_IO_CFG_EXT
309 # TODO: Can probably be removed once all chipsets have kconfig options for it.
314 config USE_WATCHDOG_ON_BOOT
322 Build board-specific VGA code.
328 Enable Unified Memory Architecture for graphics.
335 #TODO Remove this option or make it useful.
336 config HAVE_LOW_TABLES
340 This Option is unused in the code. Since two boards try to set it to
341 'n', they may be broken. We either need to make the option useful or
342 get rid of it. The broken boards are:
346 config HAVE_HIGH_TABLES
350 This variable specifies whether a given northbridge has high table
352 It is set in northbridge/*/Kconfig.
353 Whether or not the high tables are actually written by coreboot is
354 configurable by the user via WRITE_HIGH_TABLES.
356 config HAVE_ACPI_TABLES
359 This variable specifies whether a given board has ACPI table support.
360 It is usually set in mainboard/*/Kconfig.
361 Whether or not the ACPI tables are actually generated by coreboot
362 is configurable by the user via GENERATE_ACPI_TABLES.
367 This variable specifies whether a given board has MP table support.
368 It is usually set in mainboard/*/Kconfig.
369 Whether or not the MP table is actually generated by coreboot
370 is configurable by the user via GENERATE_MP_TABLE.
372 config HAVE_PIRQ_TABLE
375 This variable specifies whether a given board has PIRQ table support.
376 It is usually set in mainboard/*/Kconfig.
377 Whether or not the PIRQ table is actually generated by coreboot
378 is configurable by the user via GENERATE_PIRQ_TABLE.
380 #These Options are here to avoid "undefined" warnings.
381 #The actual selection and help texts are in the following menu.
383 config GENERATE_ACPI_TABLES
385 default HAVE_ACPI_TABLES
387 config GENERATE_MP_TABLE
389 default HAVE_MP_TABLE
391 config GENERATE_PIRQ_TABLE
393 default HAVE_PIRQ_TABLE
395 config WRITE_HIGH_TABLES
397 default HAVE_HIGH_TABLES
401 config WRITE_HIGH_TABLES
402 bool "Write 'high' tables to avoid being overwritten in F segment"
403 depends on HAVE_HIGH_TABLES
407 bool "Generate Multiboot tables (for GRUB2)"
410 config GENERATE_ACPI_TABLES
411 depends on HAVE_ACPI_TABLES
412 bool "Generate ACPI tables"
415 Generate ACPI tables for this board.
419 config GENERATE_MP_TABLE
420 depends on HAVE_MP_TABLE
421 bool "Generate an MP table"
424 Generate an MP table (conforming to the Intel MultiProcessor
425 specification 1.4) for this board.
429 config GENERATE_PIRQ_TABLE
430 depends on HAVE_PIRQ_TABLE
431 bool "Generate a PIRQ table"
434 Generate a PIRQ table for this board.
443 prompt "Add a payload"
449 Select this option if you want to create an "empty" coreboot
450 ROM image for a certain mainboard, i.e. a coreboot ROM image
451 which does not yet contain a payload.
453 For such an image to be useful, you have to use 'cbfstool'
454 to add a payload to the ROM image later.
457 bool "An ELF executable payload"
459 Select this option if you have a payload image (an ELF file)
460 which coreboot should run as soon as the basic hardware
461 initialization is completed.
463 You will be able to specify the location and file name of the
468 config FALLBACK_PAYLOAD_FILE
469 string "Payload path and filename"
470 depends on PAYLOAD_ELF
471 default "payload.elf"
473 The path and filename of the ELF executable file to use as payload.
475 # TODO: Defined if no payload? Breaks build?
476 config COMPRESSED_PAYLOAD_LZMA
477 bool "Use LZMA compression for payloads"
479 depends on PAYLOAD_ELF
481 In order to reduce the size payloads take up in the ROM chip
482 coreboot can compress them using the LZMA algorithm.
484 config COMPRESSED_PAYLOAD_NRV2B
493 bool "Add a VGA BIOS image"
495 Select this option if you have a VGA BIOS image that you would
496 like to add to your ROM.
498 You will be able to specify the location and file name of the
501 config FALLBACK_VGA_BIOS_FILE
502 string "VGA BIOS path and filename"
504 default "vgabios.bin"
506 The path and filename of the file to use as VGA BIOS.
508 config FALLBACK_VGA_BIOS_ID
509 string "VGA device PCI IDs"
513 The comma-separated PCI vendor and device ID that would associate
514 your VGA BIOS to your video card.
518 In the above example 1106 is the PCI vendor ID (in hex, but without
519 the "0x" prefix) and 3230 specifies the PCI device ID of the
520 video card (also in hex, without "0x" prefix).
523 bool "Add an MBI image"
524 depends on NORTHBRIDGE_INTEL_I82830
526 Select this option if you have an Intel MBI image that you would
527 like to add to your ROM.
529 You will be able to specify the location and file name of the
532 config FALLBACK_MBI_FILE
533 string "Intel MBI path and filename"
537 The path and filename of the file to use as VGA BIOS.
542 depends on PCI_OPTION_ROM_RUN_YABEL
545 prompt "Show graphical bootsplash"
547 depends on PCI_OPTION_ROM_RUN_YABEL
549 This option shows a graphical bootsplash screen. The grapics are
550 loaded from the CBFS file bootsplash.jpg.
552 config FALLBACK_BOOTSPLASH_FILE
553 string "Bootsplash path and filename"
554 depends on BOOTSPLASH
555 default "bootsplash.jpg"
557 The path and filename of the file to use as graphical bootsplash
558 screen. The file format has to be jpg.
560 # TODO: Turn this into a "choice".
561 config FRAMEBUFFER_VESA_MODE
562 prompt "VESA framebuffer video mode"
565 depends on BOOTSPLASH
567 This option sets the resolution used for the coreboot framebuffer and
568 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
569 some day make this a "choice".
571 config COREBOOT_KEEP_FRAMEBUFFER
572 prompt "Keep VESA framebuffer"
574 depends on BOOTSPLASH
576 This option keeps the framebuffer mode set after coreboot finishes
577 execution. If this option is enabled, coreboot will pass a
578 framebuffer entry in its coreboot table and the payload will need a
579 framebuffer driver. If this option is disabled, coreboot will switch
580 back to text mode before handing control to a payload.
586 # TODO: Better help text and detailed instructions.
588 bool "GDB debugging support"
591 If enabled, you will be able to set breakpoints for gdb debugging.
592 See src/arch/i386/lib/c_start.S for details.
596 config LIFT_BSP_APIC_ID
600 # These probably belong somewhere else, but they are needed somewhere.
601 config AP_CODE_IN_CAR
609 config ENABLE_APIC_EXT_ID
613 config WARNINGS_ARE_ERRORS
617 config ID_SECTION_OFFSET