From: Stefan REBERNIG <c0726283@ti9.(none)>
Date: Fri, 17 Dec 2010 09:35:39 +0000 (+0100)
Subject: wb extension
X-Git-Tag: bootrom_v1~44^2~26
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=e0ad83cbf694bd8c572667aca66cafadbd6c96bd

wb extension
---

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 5eb1f94..7cf1548 100644
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -12,6 +12,7 @@ use work.extension_uart_pkg.all;
 architecture behav of writeback_stage is
 
 signal data_ram_read, data_ram_read_ext : word_t;
+signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
@@ -32,8 +33,8 @@ begin
 		
 		port map (
 			clk,
-			wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
-			wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
+			data_addr(DATA_ADDR_WIDTH+1 downto 2),
+			data_addr(DATA_ADDR_WIDTH+1 downto 2),
 			wb_reg_nxt.dmem_write_en,
 			ram_data,
 			data_ram_read
@@ -141,11 +142,17 @@ end process;
 
 
 
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt)
 
 begin	
 	reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
 	reg_addr <= result_addr;
+
+	data_addr <= (others => '0');
+	
+	if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) = '1') then
+		data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+	end if;
 end process;