dt: some dependencies fixes, so it compiles with quartus

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 07da7b24afca2dc4b0a8498ff0a93a5352a8905f..242683e1ec73ca22cfcfd6c4477269b185a1965d 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -67,6 +67,9 @@ architecture behav of core_top is
                 signal sys_res_n : std_logic;
 
                 signal int_req : interrupt_t;
+
+                signal new_im_data : std_logic;
+                signal im_addr, im_data : gp_register_t;
                 
                 signal vers, vers_nxt : exec2wb_rec;
 begin
@@ -89,7 +92,10 @@ begin
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
                        int_req => int_req,
-
+               -- instruction memory program port :D
+                       new_im_data_in => new_im_data,
+                       im_addr => im_addr,
+                       im_data => im_data,
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
                        prog_cnt => prog_cnt_pin                
@@ -148,10 +154,13 @@ begin
 --
 
                        writeback_st : writeback_stage
-                generic map('0', '1')
+                generic map('0', '1', "altera")
                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3, int_req);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+                               -- instruction memory program port :D
+                               new_im_data, im_addr, im_data,
+                               sseg0, sseg1, sseg2, sseg3, int_req);
 
 
 syn: process(sys_clk, sys_res)

diff --git a/cpu/src/core_top_s3e.vhd b/cpu/src/core_top_s3e.vhd
index 51465e5155b34f10259ccde7725fd7a6ffa84395..e047c62f8dbb665f1e20b4099475780850e768e2 100644 (file)
--- a/cpu/src/core_top_s3e.vhd
+++ b/cpu/src/core_top_s3e.vhd
@@ -67,7 +67,10 @@ architecture behav of core_top is
                 signal sys_res_n : std_logic;
 
                 signal int_req : interrupt_t;
-                
+
+                signal new_im_data : std_logic;
+                signal im_addr, im_data : gp_register_t;
+
                 signal vers, vers_nxt : exec2wb_rec;
 begin
 
@@ -89,7 +92,10 @@ begin
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
                        int_req => int_req,
-
+               -- instruction memory program port :D
+                       new_im_data_in => new_im_data,
+                       im_addr => im_addr,
+                       im_data => im_data,
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
                        prog_cnt => prog_cnt_pin                
@@ -151,8 +157,10 @@ begin
                 generic map('0', '1', "s3e")
                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin,
-                               alu_jump_bit_pin,bus_tx, bus_rx, open, open, open, sseg0, sseg1, sseg2, sseg3, int_req);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+                               -- instruction memory program port :D
+                               new_im_data, im_addr, im_data,
+                               sseg0, sseg1, sseg2, sseg3, int_req);
 
 
 syn: process(sys_clk, sys_res)

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index 0bdcaca896d5b82b17fbbe6bd911ecbdec7fe861..e1135d411ac9ed4cfda5a391d7f9c6de13213815 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -141,7 +141,7 @@ begin
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
-                generic map('0', '1')
+                generic map('0', '1', "altera")
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);

diff --git a/dt/dt.qsf b/dt/dt.qsf
index a9102b02dd2aa7a1a62ce2916547b292a1ce5c2b..5916bb33f6b7c172bd8150f10e4fedf2dd827de8 100644 (file)
--- a/dt/dt.qsf
+++ b/dt/dt.qsf
@@ -104,6 +104,12 @@ set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
@@ -125,4 +131,6 @@ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
+
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file