spartan3e: at least it compiles

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index dc6f8cebfe888a8700ec83415853d5b27ec876b0..c27a5a0ca32c93295b79258dbc6add5023bb8d22 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -123,8 +123,8 @@ package core_pkg is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic
-                       
+                       LOGIC_ACT : std_logic;
+                       FPGATYPE : string
                        );
        port(
                --System inputs

diff --git a/cpu/src/core_top_s3e.vhd b/cpu/src/core_top_s3e.vhd
new file mode 100644 (file)
index 0000000..51465e5
--- /dev/null
+++ b/cpu/src/core_top_s3e.vhd
@@ -0,0 +1,209 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+use work.extension_pkg.all;
+
+entity core_top is
+
+       port(
+               --System input pins
+                  sys_res : in std_logic;
+                       sys_clk : in std_logic;
+--                     result : out gp_register_t;
+--                     reg_wr_data : out gp_register_t
+                 -- uart
+                       bus_tx : out std_logic;
+                       bus_rx : in std_logic;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
+               );
+
+end core_top;
+
+architecture behav of core_top is
+
+               constant SYNC_STAGES : integer := 2;
+               constant RESET_VALUE : std_logic := '0';
+
+               signal jump_result : instruction_addr_t;
+               signal jump_result_pin : instruction_addr_t;
+               signal prediction_result_pin : instruction_addr_t;
+               signal branch_prediction_bit_pin : std_logic;
+               signal alu_jump_bit_pin : std_logic;
+               signal instruction_pin : instruction_word_t;
+               signal prog_cnt_pin : instruction_addr_t;
+
+               signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+               signal reg_wr_data_pin : gp_register_t;
+               signal reg_we_pin : std_logic;
+               signal to_next_stage : dec_op;
+
+--             signal reg1_rd_data_pin : gp_register_t;
+--             signal reg2_rd_data_pin : gp_register_t;
+
+                 signal result_pin : gp_register_t;--reg
+                 signal result_addr_pin : gp_addr_t;--reg
+                 signal addr_pin : word_t; --memaddr
+                 signal data_pin : gp_register_t; --mem data --ureg
+                 signal alu_jump_pin : std_logic;--reg
+                 signal brpr_pin  : std_logic;  --reg
+                 signal wr_en_pin : std_logic;--regop --reg
+                 signal dmem_pin  : std_logic;--memop
+                 signal dmem_wr_en_pin : std_logic;
+                 signal hword_pin  : std_logic;
+                 signal byte_s_pin : std_logic;
+                                
+                signal gpm_in_pin : extmod_rec;
+                signal gpm_out_pin : gp_register_t;
+                signal nop_pin : std_logic;
+                
+                signal sync : std_logic_vector(1 to SYNC_STAGES);
+                signal sys_res_n : std_logic;
+
+                signal int_req : interrupt_t;
+                
+                signal vers, vers_nxt : exec2wb_rec;
+begin
+
+       fetch_st : fetch_stage
+               generic map (
+       
+                       '0',
+                       '1'
+               )
+               
+               port map (
+               --System inputs
+                       clk => sys_clk, --: in std_logic;
+                       reset => sys_res_n, --: in std_logic;
+               
+               --Data inputs
+                       jump_result => jump_result_pin, --: in instruction_addr_t;
+                       prediction_result => prediction_result_pin, --: in instruction_addr_t;
+                       branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
+                       alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+                       int_req => int_req,
+
+               --Data outputs
+                       instruction => instruction_pin, --: out instruction_word_t
+                       prog_cnt => prog_cnt_pin                
+               );
+
+       decode_st : decode_stage
+               generic map (
+                       -- active reset value
+                       '0',
+                       -- active logic value
+                       '1'
+                       
+                       )
+               port map (
+               --System inputs
+                       clk => sys_clk, --: in std_logic;
+                       reset => sys_res_n, -- : in std_logic;
+
+               --Data inputs
+                       instruction => instruction_pin, --: in instruction_word_t;
+                       prog_cnt => prog_cnt_pin,
+                       reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+                       reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
+                       reg_we => reg_we_pin, --: in std_logic;
+                       nop => nop_pin,
+
+               --Data outputs
+                       branch_prediction_res => prediction_result_pin, --: instruction_word_t;
+                       branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+                       to_next_stage => to_next_stage
+               );
+
+          exec_st : execute_stage
+                generic map('0')
+                port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
+
+
+                       vers_nxt.result <= result_pin;
+                       vers_nxt.result_addr <= result_addr_pin;
+                       vers_nxt.address <= addr_pin;
+                       vers_nxt.ram_data <= data_pin;
+                       vers_nxt.alu_jmp <= alu_jump_pin;
+                       vers_nxt.br_pred <= brpr_pin;
+                       vers_nxt.write_en <= wr_en_pin;
+                       vers_nxt.dmem_en <= dmem_pin;
+                       vers_nxt.dmem_write_en <= dmem_wr_en_pin;
+                       vers_nxt.hword <= hword_pin;
+                       vers_nxt.byte_s <= byte_s_pin;
+                                                                        
+--          writeback_st : writeback_stage
+--                generic map('0', '1')
+--                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+--                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+--                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+--
+
+                       writeback_st : writeback_stage
+                generic map('0', '1', "s3e")
+                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin,
+                               alu_jump_bit_pin,bus_tx, bus_rx, open, open, open, sseg0, sseg1, sseg2, sseg3, int_req);
+
+
+syn: process(sys_clk, sys_res)
+
+begin
+
+       if sys_res = '0' then
+--                     vers.result <= (others => '0');
+--                     vers.result_addr <= (others => '0');
+--                     vers.address <= (others => '0');
+--                     vers.ram_data <= (others => '0');
+--                     vers.alu_jmp <= '0';
+--                     vers.br_pred <= '0';
+--                     vers.write_en <= '0';
+--                     vers.dmem_en <= '0';
+--                     vers.dmem_write_en <= '0';
+--                     vers.hword <= '0';
+--                     vers.byte_s <= '0';
+       
+               sync <= (others => '0');
+       
+       elsif rising_edge(sys_clk) then
+--             vers <= vers_nxt;
+                       sync(1) <= sys_res;
+                       for i in 2 to SYNC_STAGES loop
+                               sync(i) <= sync(i - 1);
+                       end loop;
+                               
+       end if;
+       
+end process;
+
+sys_res_n <= sync(SYNC_STAGES);
+       
+--init : process(all)
+
+--begin
+--     jump_result_pin <= (others => '0');
+--     alu_jump_bit_pin <= '0';
+--     reg_w_addr_pin <= (others => '0');
+--     reg_wr_data_pin <= (others => '0');
+--     reg_we_pin <= '0';
+       
+--end process;
+       
+--     result <= result_pin;
+       nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
+
+       jump_result <= prog_cnt_pin; --jump_result_pin;
+--     sys_res <= '1';
+
+--     reg_wr_data <= reg_wr_data_pin;
+
+end behav;

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
index 906f175f8ca9d552899f45225cd24042a05a48fe..c2d3cdd21c640bdbf32b0d4664684c01f9ba7b50 100644 (file)
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -43,6 +43,17 @@ package mem_pkg is
        );
        end component r_w_ram_be;
 
+       component ram_xilinx is
+       generic ( ADDR_WIDTH : integer range 1 to integer'high);
+       port(clk : in std_logic;
+               addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+               be : in std_logic_vector(3 downto 0);
+               we : in std_logic; -- dummy :/
+               wdata : in std_logic_vector(31 downto 0);
+               q : out std_logic_vector(31 downto 0)
+       );
+       end component ram_xilinx;
+
        component rom is
        generic (
                                ADDR_WIDTH : integer range 1 to integer'high;

diff --git a/cpu/src/ram_xilinx.vhd b/cpu/src/ram_xilinx.vhd
new file mode 100644 (file)
index 0000000..0166b55
--- /dev/null
+++ b/cpu/src/ram_xilinx.vhd
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ram_xilinx is
+       generic ( ADDR_WIDTH : integer range 1 to integer'high);
+       port(clk : in std_logic;
+               addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+               be : in std_logic_vector(3 downto 0);
+               we : in std_logic; -- dummy :/
+               wdata : in std_logic_vector(31 downto 0);
+               q : out std_logic_vector(31 downto 0)
+       );
+end;

diff --git a/cpu/src/ram_xilinx_b.vhd b/cpu/src/ram_xilinx_b.vhd
new file mode 100644 (file)
index 0000000..a18b998
--- /dev/null
+++ b/cpu/src/ram_xilinx_b.vhd
@@ -0,0 +1,321 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+architecture logic of ram_xilinx is
+       constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
+       constant ONE : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
+begin
+
+   RAMB16_S9_inst0 : RAMB16_S9 -- 2k x 8bit (+ 1 bit parity)
+   generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DO   => q(31 downto 24),
+      DOP  => open, 
+      ADDR => addr(ADDR_WIDTH-1 downto 0),
+      CLK  => clk, 
+      DI   => wdata(31 downto 24),
+      DIP  => ZERO(0 downto 0),
+      EN   => ONE(0),
+      SSR  => ZERO(0),
+      WE   => be(3));
+
+   RAMB16_S9_inst1 : RAMB16_S9
+   generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DO   => q(23 downto 16),
+      DOP  => open, 
+      ADDR => addr(12 downto 2),
+      CLK  => clk, 
+      DI   => wdata(23 downto 16),
+      DIP  => ZERO(0 downto 0),
+      EN   => ONE(0),
+      SSR  => ZERO(0),
+      WE   => be(2));
+
+   RAMB16_S9_inst2 : RAMB16_S9
+   generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DO   => q(15 downto 8),
+      DOP  => open, 
+      ADDR => addr(12 downto 2),
+      CLK  => clk, 
+      DI   => wdata(15 downto 8),
+      DIP  => ZERO(0 downto 0),
+      EN   => ONE(0),
+      SSR  => ZERO(0),
+      WE   => be(1));
+
+   RAMB16_S9_inst3 : RAMB16_S9
+   generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DO   => q(7 downto 0),
+      DOP  => open, 
+      ADDR => addr(12 downto 2),
+      CLK  => clk, 
+      DI   => wdata(7 downto 0),
+      DIP  => ZERO(0 downto 0),
+      EN   => ONE(0),
+      SSR  => ZERO(0),
+      WE   => be(0));
+end;

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index aacba01de09a655846e40b1ba7b08d0b92ffbf10..9ec598638530aa97708967dca32b9ac78210de10 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -10,8 +10,8 @@ entity writeback_stage is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic
-                       
+                       LOGIC_ACT : std_logic;
+                       FPGATYPE : string
                        );
        port(
                --System inputs

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 7b57d4565c89592569fb72f709353497718d054d..fd26a297b8e5727e9f5c2d975c600cb9b35115fd 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -34,6 +34,22 @@ begin
        ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
+       spartan3e: if FPGATYPE = "s3e" generate
+               data_ram : ram_xilinx
+               generic map (
+                       DATA_ADDR_WIDTH
+               )
+               port map (
+                       clk,
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.byte_en,
+                       dmem_we,
+                       wb_reg_nxt.data, --ram_data,
+                       data_ram_read
+               );
+       end generate;
+       -- else generate gibt es erst mit vhdl 2008 ...
+       altera: if FPGATYPE /= "s3e" generate
        data_ram : r_w_ram_be
                generic map (
                        DATA_ADDR_WIDTH
@@ -48,6 +64,7 @@ begin
                        wb_reg_nxt.data, --ram_data,
                        data_ram_read
                );
+       end generate;
 
 uart : extension_uart 
        generic map(
@@ -77,6 +94,7 @@ imp : extension_imp
                        new_im_data_out
                );
        
+       altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
        generic map(
                RESET_VALUE
@@ -90,6 +108,7 @@ sseg : extension_7seg
                sseg2,
                sseg3
                );
+       end generate;
 
 interrupt : extension_interrupt
        generic map(

diff --git a/spartan3e/.gitignore b/spartan3e/.gitignore
new file mode 100644 (file)
index 0000000..6536cc7
--- /dev/null
+++ b/spartan3e/.gitignore
@@ -0,0 +1,30 @@
+*.ngc_xst.xrpt
+*.prj
+*.srp
+xst/
+*.bld
+*.ngc
+*_ngdbuild.xrpt
+*.mrp
+*.ncd
+*.ngd
+*.ngm
+*.pad
+*.par
+*.pcf
+*.ptwx
+*.twr
+*.twx
+*.unroutes
+*.xpi
+*_map.xrpt
+*_pad.csv
+*_pad.txt
+*_par.xrpt
+*_summary.xml
+*_usage.xml
+generated/
+smartpreview.twr
+xlnx_auto_0_xdb/
+*.log
+_xmsgs/

diff --git a/spartan3e/ISE_scripts/core_top.scrs b/spartan3e/ISE_scripts/core_top.scrs
new file mode 100644 (file)
index 0000000..6315271
--- /dev/null
+++ b/spartan3e/ISE_scripts/core_top.scrs
@@ -0,0 +1,7 @@
+run
+-ifn core_top.prj
+-ifmt VHDL
+-ofn core_top.ngc
+-ofmt NGC -p XC3S500E-FG320-4
+-opt_mode Area
+-opt_level 2

diff --git a/spartan3e/ISE_scripts/loadjtag.cmds b/spartan3e/ISE_scripts/loadjtag.cmds
new file mode 100644 (file)
index 0000000..2f521d0
--- /dev/null
+++ b/spartan3e/ISE_scripts/loadjtag.cmds
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignFile -p 1 -file generated/core_top.bit
+program -e -p 1
+quit

diff --git a/spartan3e/ISE_scripts/loadprom.cmds b/spartan3e/ISE_scripts/loadprom.cmds
new file mode 100644 (file)
index 0000000..c98c700
--- /dev/null
+++ b/spartan3e/ISE_scripts/loadprom.cmds
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignFile -p 2 -file generated/core_top.mcs
+program -e -p 2 -v
+quit

diff --git a/spartan3e/ISE_scripts/makeprom.cmds b/spartan3e/ISE_scripts/makeprom.cmds
new file mode 100644 (file)
index 0000000..4cece00
--- /dev/null
+++ b/spartan3e/ISE_scripts/makeprom.cmds
@@ -0,0 +1,8 @@
+setMode -pff
+setSubmode -pffserial
+addPromDevice -p 1 -name xcf04s
+addDesign -version 0 -name 0
+addDeviceChain -index 0
+addDevice -p 1 -file generated/core_top.bit
+generate -format mcs -fillvalue FF -output generated/core_top.mcs
+quit

diff --git a/spartan3e/Makefile b/spartan3e/Makefile
new file mode 100644 (file)
index 0000000..eafb800
--- /dev/null
+++ b/spartan3e/Makefile
@@ -0,0 +1,116 @@
+SHELL := bash
+
+VHDL_DIR := ../cpu/src
+PROJ_VHDL = \
+       core_top_s3e.vhd \
+       alu_b.vhd \
+       alu_pkg.vhd \
+       alu.vhd \
+       common_pkg.vhd \
+       core_pkg.vhd \
+       decoder_b.vhd \
+       decoder.vhd \
+       decode_stage_b.vhd \
+       decode_stage.vhd \
+       exec_op/add_op_b.vhd \
+       exec_op/and_op_b.vhd \
+       exec_op/or_op_b.vhd \
+       exec_op/shift_op_b.vhd \
+       exec_op/xor_op_b.vhd \
+       exec_op.vhd \
+       execute_stage_b.vhd \
+       execute_stage.vhd \
+       extension_b.vhd \
+       extension_interrupt_b.vhd \
+       extension_interrupt.vhd \
+       extension_pkg.vhd \
+       extension_uart_b.vhd \
+       extension_uart_pkg.vhd \
+       extension_uart.vhd \
+       extension_7seg_b.vhd \
+       extension_7seg_pkg.vhd \
+       extension_7seg.vhd \
+       extension_imp_b.vhd \
+       extension_imp_pkg.vhd \
+       extension_imp.vhd \
+       extension.vhd \
+       fetch_stage_b.vhd \
+       fetch_stage.vhd \
+       mem_pkg.vhd \
+       r2_w_ram_b.vhd \
+       r2_w_ram.vhd \
+       rom_b.vhd \
+       rom.vhd \
+       rs232_rx_arc.vhd \
+       rs232_rx.vhd \
+       rs232_tx_arc.vhd \
+       rs232_tx.vhd \
+       ram_xilinx.vhd \
+       ram_xilinx_b.vhd \
+       r_w_ram_b.vhd \
+       r_w_ram.vhd \
+       rw_r_ram_b.vhd \
+       rw_r_ram.vhd \
+       writeback_stage_b.vhd \
+       writeback_stage.vhd
+
+PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
+
+NAME := core_top
+
+
+all: generated/$(NAME).mcs
+
+generated: 
+       rm -rf generated
+       mkdir generated
+
+clean:
+       rm -rf *.o *.cf tb *.vcd $(NAME) $(SIM_TOP) *.ghw
+       rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
+       rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
+       rm -f *.bld *.ncd *.twr *.drc
+       rm -f *.map *.xrpt *.log *.twx *.xml *.ptwx
+       rm -rf xst $(NAME).prj
+       rm -rf generated/
+       rm -rf xlnx_auto_0_xdb _xmsgs
+
+#Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
+
+# create an ISE project file from the list of VHDL files
+$(NAME).prj: $(PROJ_VHDL)
+       echo $(PROJ_VHDL) |tr " " "\n">$(NAME).prj
+
+bitfile: generated step0 step1 step2 step3 step4 step5
+
+step0: $(NAME).prj 
+       xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
+step1:
+       ngdbuild -nt on -uc spartan3e.ucf $(NAME).ngc $(NAME).ngd
+step2:
+       map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
+step3:
+       par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
+step4:
+       trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
+step5:
+       bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
+
+generated/$(NAME).bit: bitfile
+
+jtag: generated/$(NAME).bit
+       impact -batch ISE_scripts/loadjtag.cmds
+
+mcs: generated/$(NAME).bit
+       impact -batch ISE_scripts/makeprom.cmds
+
+generated/$(NAME).mcs: mcs
+
+load: generated/$(NAME).mcs
+       impact -batch ISE_scripts/loadprom.cmds
+
+impact:
+       impact
+
+ise: $(NAME).prj
+       ise

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
new file mode 100644 (file)
index 0000000..4cc5151
--- /dev/null
+++ b/spartan3e/spartan3e.ucf
@@ -0,0 +1,279 @@
+#####################################################
+### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
+#####################################################
+# ==== Analog-to-Digital Converter (ADC) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Programmable Gain Amplifier (AMP) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+#NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Pushbuttons (BTN) ====
+#NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
+#NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
+NET "sys_res" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
+#NET "btn_a" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
+# ==== Clock inputs (CLK) ====
+NET "sys_clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+NET "sys_clk" PERIOD = 20 ns HIGH 40 % ;
+#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+# ==== Digital-to-Analog Converter (DAC) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+# ==== 1-Wire Secure EEPROM (DS)
+#NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+# ==== Ethernet PHY (E) ====
+#NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
+#NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
+#NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+#NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
+#NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<2>" LOC = "R5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<3>" LOC = "T5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
+#NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+#NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+#NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
+# ==== FX2 Connector (FX2) ====
+#NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
+#NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J1 6-pin accessory header
+#NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J2 6-pin accessory header
+#NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J4 6-pin accessory header
+#NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# The discrete LEDs are shared with the following 8 FX2 connections
+#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# ==== 6-pin header J1 ====
+# These are shared connections with the FX2 connector
+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== 6-pin header J2 ====
+# These are shared connections with the FX2 connector
+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== 6-pin header J4 ====
+# These are shared connections with the FX2 connector
+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== Character LCD (LCD) ====
+#NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# LCD data connections are shared with StrataFlash connections SF_D<11:8>
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# ==== Discrete LEDs (LED) ====
+# These are shared connections with the FX2 connector
+#NET "LED0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+# ==== PS/2 Mouse/Keyboard Port (PS2) ====
+#NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 ;
+#NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
+# ==== Rotary Pushbutton Switch (ROT) ====
+#NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
+# ==== RS-232 Serial Ports (RS232) ====
+NET "bus_rx" LOC = "E8" | IOSTANDARD = LVTTL ;
+NET "bus_tx" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
+#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
+#NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
+# Path to allow connection to top DCM connection
+#NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
+# Prohibit VREF pins
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
+#NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+#NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# ==== STMicro SPI serial Flash (SPI) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
+#NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Slide Switches (SW) ====
+#NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
+# ==== VGA Port (VGA) ====
+#NET "b<0>" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "g<0>" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "hsync_n" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "r<0>" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "vsync_n" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+# ==== Xilinx CPLD (XC) ====
+#NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
+#NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
+#NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "sys_clk" TNM_NET = "sys_clk";
+#NET "clk_reg1" TNM_NET = "clk_reg1";
+#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;