From da7281936586577a2bcc09269a22bade1f9db251 Mon Sep 17 00:00:00 2001 From: Stefan Date: Sun, 14 Nov 2010 16:26:08 +0100 Subject: [PATCH] =?utf8?q?gitignore=20f=C3=BCr=20sim?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- cpu/sim/.gitignore | 3 +++ cpu/src/fetch_stage_b.vhd | 6 +++++- cpu/src/r2_w_ram_b.vhd | 7 ++++++- cpu/src/r_w_ram_b.vhd | 6 +++++- 4 files changed, 19 insertions(+), 3 deletions(-) create mode 100644 cpu/sim/.gitignore diff --git a/cpu/sim/.gitignore b/cpu/sim/.gitignore new file mode 100644 index 0000000..891db2f --- /dev/null +++ b/cpu/sim/.gitignore @@ -0,0 +1,3 @@ +*.ini +*.wlf +/work/* diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd index e774901..67dde3c 100644 --- a/cpu/src/fetch_stage_b.vhd +++ b/cpu/src/fetch_stage_b.vhd @@ -45,13 +45,17 @@ begin end process; -asyn: process(instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data) +asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data) begin instruction <= instr_rd_data; instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1); + if (reset = RESET_VALUE) then + instr_r_addr_nxt <= (others => '0'); + end if; + if (alu_jump_bit = LOGIC_ACT) then instr_r_addr_nxt <= jump_result; elsif (branch_prediction_bit = LOGIC_ACT) then diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd index 84a3a94..3c71ade 100644 --- a/cpu/src/r2_w_ram_b.vhd +++ b/cpu/src/r2_w_ram_b.vhd @@ -10,7 +10,12 @@ architecture behaviour of r2_w_ram is subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; - signal ram : RAM_TYPE := (others=> x"00000001"); + signal ram : RAM_TYPE := ( + 0 => x"00000010", + 1 => x"00110010", + 2 => x"000000FF", + 3 => x"00AB00BA", + others=> x"00000000"); begin process(clk) diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 9e530fa..f033885 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -10,7 +10,11 @@ architecture behaviour of r_w_ram is subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; - signal ram : RAM_TYPE := ((others => b"11100000000000001001000000000000")); + signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", + 1 => "11100000000000001001000000000000", + 2 => "11100000000010001001000000000000", + 3 => "11100001000110010111011001101100", + others => x"00000000"); begin process(clk) -- 2.25.1