vcom -work work ../src/alu.vhd
vcom -work work ../src/alu_b.vhd
+vcom -work work ../src/extension_pkg.vhd
+vcom -work work ../src/gpm_pkg.vhd
-vcom -work work ../src/gpm.vhd
-vcom -work work ../src/gpm_b.vhd
+#vcom -work work ../src/gpm.vhd
+#vcom -work work ../src/gpm_b.vhd
vcom -work work ../src/extension_pkg.vhd
vcom -work work ../src/extension.vhd
cond : in condition_t;\r
op_group : in op_info_t;\r
left_operand : in gp_register_t;\r
- right_operand : in gp_register_t;
- displacement : in gp_register_t;
+ right_operand : in gp_register_t;\r
+ displacement : in gp_register_t;\r
prog_cnt : in instr_addr_t;\r
+ brpr : in std_logic;\r
op_detail : in op_opt_t;\r
alu_state : in alu_result_rec;\r
- alu_result : out alu_result_rec;
- addr : out word_t; --memaddr
+ alu_result : out alu_result_rec;\r
+ addr : out word_t; --memaddr\r
data : out gp_register_t --mem data --ureg\r
);\r
\r
); \r
end component exec_op;\r
\r
- signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
+ signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
signal left, right : gp_register_t;\r
\r
begin\r
shift_inst : entity work.exec_op(shift_op)\r
port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
\r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr)\r
variable result_v : alu_result_rec;\r
variable res_prod : std_logic;\r
variable cond_met : std_logic;\r
- variable mem_en : std_logic;
- variable mem_op : std_logic;
- variable alu_jmp : std_logic;\r
+ variable mem_en : std_logic;\r
+ variable mem_op : std_logic;\r
+ variable alu_jump : std_logic;\r
+ variable nop : std_logic;\r
begin\r
result_v := alu_state;\r
\r
res_prod := '1';\r
- mem_en := '0';
- mem_op := '0';
+ mem_en := '0';\r
+ mem_op := '0';\r
alu_jump := '0';\r
-
- left <= left_operand;
- right <= right_operand;
-
- addr <= add_result.result;
+ \r
+ left <= left_operand;\r
+ right <= right_operand;\r
+\r
+ addr <= add_result.result;\r
data <= right_operand;\r
-
- result_v.result := add_result.result;
+ \r
+ result_v.result := add_result.result;\r
\r
case cond is\r
when COND_NZERO =>\r
cond_met := '0';\r
when others => null;\r
end case;\r
-
- cond_met := cond_met and (alu_state.alu_jmp xnor alu_state.brpr);
+ \r
+ nop := (alu_state.alu_jump xnor alu_state.brpr);\r
+ cond_met := cond_met and nop;\r
\r
case op_group is\r
when ADDSUB_OP =>\r
when XOR_OP =>\r
result_v := xor_result;\r
when SHIFT_OP =>\r
- result_v := shift_result;
- when LDST_OP =>
- res_prod := '0';
- mem_op := '1';
- if op_detail(IMM_OPT) = '1' then
- result_v.result := right_operand;
- res_prod := '1';
- mem_op := '0';
- end if;
- if op_detail(ST_OPT) = '1' then
- right <= displacement;
- mem_en := '1';
- end if;
- when JMP_OP =>
- if op_detail(JMP_REG_OPT) = '0' then
- left <= prog_cnt;
- end if;
- result_v.alu_jmp := '1';
+ result_v := shift_result;\r
+ when LDST_OP =>\r
+ res_prod := '0';\r
+ mem_op := '1';\r
+ if op_detail(IMM_OPT) = '1' then\r
+ result_v.result := right_operand;\r
+ res_prod := '1';\r
+ mem_op := '0';\r
+ end if;\r
+ if op_detail(ST_OPT) = '1' then\r
+ right <= displacement;\r
+ mem_en := '1';\r
+ end if;\r
+ when JMP_OP =>\r
+ if op_detail(JMP_REG_OPT) = '0' then\r
+ left <= prog_cnt;\r
+ end if;\r
+ alu_jump := '1';\r
when JMP_ST_OP => null;\r
end case;\r
\r
end if;\r
\r
result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
- result_v.mem_en := mem_en and cond_met;
- result_v.mem_op := mem_op and cond_met;
- result_v.alu_jmp := alu_jmp and cond_met;
+ result_v.mem_en := mem_en and cond_met;\r
+ result_v.mem_op := mem_op and cond_met;\r
+ result_v.alu_jump := alu_jump and cond_met;\r
+ result_v.brpr := brpr and nop;\r
\r
+ if (result_v.alu_jump = '0') and (brpr = '1') then\r
+ result_v.result := (others => '0');\r
+ result_v.result(prog_cnt'range) := std_logic_vector(unsigned(prog_cnt)+1);\r
+ --result_v.reg_op := '1';\r
+ end if;\r
+\r
alu_result <= result_v;\r
\r
end process calc; \r
right_operand : in gp_register_t;
displacement : in gp_register_t;
prog_cnt : in instr_addr_t;
+ brpr : in std_logic;
op_detail : in op_opt_t;
alu_state : in alu_result_rec;
alu_result : out alu_result_rec;
subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
+ subtype instr_addr_t is instruction_addr_t;
subtype gp_addr_t is std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
-- end record;
-- output logic incl. bypassing reg-file
-output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data, nop)
begin
to_next_stage.src1 <= reg1_rd_data;
to_next_stage.src2 <= reg2_rd_data;
+ if (nop = '1') then
+ to_next_stage.condition <= "1111";
+ end if;
+
end process;
branch_prediction_bit <= '0';
if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
- branch_prediction_res <= instr_spl.immediate; --both 32 bit
+ branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
branch_prediction_bit <= '1';
end if;
alu_inst : alu
port map(clk, reset, condition, op_group,
- left_operand, right_operand, dec_instr.displacement, op_detail, alu_state, alu_nxt,addr,data);
+ left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, alu_nxt,addr,data);
- alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0');
+ alu_state <= (reg.result,dec_instr.daddr,psw,reg.alu_jump,reg.brpr,'0','0','0','0','0','0');
if reset = RESET_VALUE then
use work.common_pkg.all;
use work.extension_pkg.all;
use work.alu_pkg.all;
-use work.gpm_pkg.all;
+--use work.gpm_pkg.all;
entity extension_gpm is
use work.common_pkg.all;
use work.alu_pkg.all;
-use work.gpm_pkg.all;
+--use work.gpm_pkg.all;
package extension_pkg is
end if;
if (alu_jump_bit = LOGIC_ACT) then
- instr_r_addr_nxt <= jump_result;
+ instr_r_addr_nxt <= jump_result;
+ instruction(31 downto 28) <= "1111";
elsif (branch_prediction_bit = LOGIC_ACT) then
instr_r_addr_nxt <= prediction_result;
end if;
end process;
-prog_cnt <= std_logic_vector(unsigned(instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0)) + 1;
+prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+prog_cnt(31 downto 11) <= (others => '0');
end behav;
- nop_pin <= (alu_jump_bit_pin xor brpr_pin);
+ nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
-------------------------------------------------------------------------------
-- generate simulation clock
-- r0 = 0, r1 = 1, r2 = 3, r3 = A
- signal ram : RAM_TYPE := ( 0 => "11101101000010000000000000111000", -- r1 = 7
- 1 => "11101101000100000000000000101000", -- r2 = 5
- 2 => "11101101000110000000000000100000", -- r3 = 4
- 3 => "11100000001000010001100000000000", -- r4 = r2 + r3
- 4 => "11100010001010100000100000000000", -- r5 = r4 and r1
- 5 => "11100111101010100000000000000001", -- stw r5,r4,1
- 6 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001
+ signal ram : RAM_TYPE := (
+ 1 => "11101101000010000000000000111000", -- r1 = 7
+ 2 => "11101101000100000000000000101000", -- r2 = 5
+ 3 => "11101101000110000000000000100000", -- r3 = 4
+ 4 => "11100000001000010001100000000000", -- r4 = r2 + r3
+ 5 => "11100010001010100000100000000000", -- r5 = r4 and r1
+
+ 6 => "11100001000000000000000000001000", -- r0 = r0 + 1
+ 7 => "11101100100000000000000000010000", -- cmpi r0 , 2 => 2-2 => 1001
+
+ 8 => "00001011011111111111110010000011", -- jump -7
+ 9 => "11101011000000000000000010000010", -- jump +1
+
+ 10 => "11100111101010100000000000000001", -- stw r5,r4,1
+ 11 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001
+
+ 0 => "11101101000000000000000000000000", -- r0 = 0
+
others => x"F0000000");
end if;
end if;
- jump <= alu_jmp xor br_pred;
+ jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
+
+ if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
+ jump <= '1';
+ end if;
+
jump_addr <= result;
if ((alu_jmp and wb_reg.dmem_en) = '1') then
jump_addr <= data_ram_read;