Added missing signals to sensitivity and extended writeback

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index f0eda881851fd219ba4bf32134051457331213c5..9a0749155f5c5070eacfb780f779a2516fb67f29 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -188,6 +188,9 @@ begin
                --result_v.reg_op := '1';\r
        end if;\r
 \r
+       -- if result_v.mem_op = '0' then --- do this if selecting enable for extension modules is too slow.\r
+               -- addr <= (others => '0');\r
+       -- end if;\r
        alu_result <= result_v;\r
        pinc <= pinc_v;\r
        pwr_en <= pwr_en_v;\r

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 1e2a42d776c696fcae497673e3cdad60aa99e3f8..b223718326fa32e23875eda6da0a449742c1fb81 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -18,7 +18,8 @@ package common_pkg is
        subtype word_t  is std_logic_vector(WORD_WIDTH-1 downto 0);
 
        subtype gp_register_t is word_t;
-
+       
+       subtype byte_en_t is std_logic_vector((gp_register_t'length/byte_t'length-1) downto 0); 
        
        constant REG_ZERO : gp_register_t := (others => '0');
 
@@ -134,6 +135,8 @@ package common_pkg is
                dmem_write_en : std_logic;      --ureg
                hword : std_logic;              --ureg
                byte_s : std_logic;
+               byte_en : byte_en_t;
+               data : gp_register_t;
        end record;
        
        type exec2wb_rec is record

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 5352332ddcc9744162ed4eaefa41bf07ea3bdc04..7ece8f1decf6b0e8768b396012ee180e33c613db 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -140,8 +140,8 @@ begin
 
                        writeback_st : writeback_stage
                 generic map('0', '1')
-                port map(sys_clk, sys_res, vers.result, vers.result_addr, vers.address, vers.ram_data, vers.alu_jmp, vers.br_pred, 
-                vers.write_en, vers.dmem_en, vers.dmem_write_en, vers.hword, vers.byte_s,
+                port map(sys_clk, sys_res, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 
 

diff --git a/cpu/src/exec_op/add_op_b.vhd b/cpu/src/exec_op/add_op_b.vhd
index 331bb2968edf4bf5f52f20832d3d80a2c9de619a..44c1b928d01f411375fb2d6667ec6f7d87e77e31 100644 (file)
--- a/cpu/src/exec_op/add_op_b.vhd
+++ b/cpu/src/exec_op/add_op_b.vhd
@@ -24,7 +24,7 @@ calc: process(left_operand, right_operand, alu_state, sub, addc)
 begin
                alu_result_v := alu_state;
                addcarry := (others => '0');
-               addcarry(0):= (alu_state.status.carry and addc) or sub;
+               addcarry(0):= (alu_state.status.carry and addc) or (sub and not(addc));
                if sub = '1' then
                        carry_res := unsigned('0' & left_operand)+unsigned('0' & not(right_operand))+addcarry;
                else

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index 20cf1cd02bce9d80f3444a7a7dace5baba84ccdd..35c13d747ce60614c6c12cb5c2f344294e616f4d 100644 (file)
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -21,7 +21,7 @@ subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);
         type extmod_rec is record
                 sel   : std_logic;
                 wr_en : std_logic;
-                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
+                byte_en : byte_en_t;
                 data : gp_register_t;
                 addr : ext_addr_t;     
         end record; 

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
old mode 100644 (file)
new mode 100755 (executable)
index 6f2c9c4..1a59b1e
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -18,13 +18,16 @@ signal data_addr : word_t;
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
 signal ext_uart,ext_timer,ext_gpmp,ext_7seg :  extmod_rec;
+signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t;
 
-signal sel_nxt, dmem_we, bus_rx :std_logic;
+signal sel_nxt, dmem_we, bus_rx, ext_anysel : std_logic;
 
 signal calc_mem_res : gp_register_t;
 
 begin
 
+       ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
+       ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
        data_ram : r_w_ram
                generic map (
@@ -49,7 +52,7 @@ uart : extension_uart
                        clk ,
                        reset,
                        ext_uart,
-                       data_ram_read_ext,
+                       ext_uart_out,
                        bus_rx,
                        bus_tx
                );
@@ -79,6 +82,9 @@ begin
                wb_reg.hword <= '0';
                wb_reg.byte_s <= '0';
                bus_rx <= '1';
+               
+               wb_reg.byte_en <= (others => '0');
+               wb_reg.data <= (others =>'0');
        elsif rising_edge(clk) then
                wb_reg <= wb_reg_nxt;
                bus_rx <= '1';
@@ -95,8 +101,8 @@ end process;
 
 
 
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en)
-
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en, ram_data)
+variable byte_en : byte_en_t;
 begin
        wb_reg_nxt.address <= address;
        wb_reg_nxt.dmem_en <= dmem_en;
@@ -105,28 +111,51 @@ begin
        wb_reg_nxt.byte_s <= byte_s;
 
        calc_mem_res <= result; --(others => '0');
-
-       if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then   -- ram read operation --alu_jmp = '0' and 
-               calc_mem_res <= data_ram_read;
-               if (wb_reg.hword = '1') then
-                       calc_mem_res <= (others => '0');
-                       if (wb_reg.address(1) = '1') then
-                               calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16);
-                       else
-                               calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0);
-                       end if;
-               end if;
-               if (wb_reg.byte_s = '1') then
-                       calc_mem_res <= (others => '0');
-                       case wb_reg.address(1 downto 0) is
-                               when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0);
-                               when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8);
-                               when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16);
-                               when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24);
-                               when others => null;
+       
+       wb_reg_nxt.data <= ram_data;
+       byte_en := (others => '0');
+       if dmem_en = '1' then
+               if hword = '1' then
+                       case address(BYTEADDR-1 downto 0) is
+                       when "00" => byte_en(1 downto 0) := "11";
+                       when "10" => byte_en(3 downto 2) := "11";
+                       when others => null;
                        end case;
-               end if; 
+               elsif byte_s = '1' then
+                       case address(BYTEADDR-1 downto 0) is
+                       when "00" => byte_en(0) := '1';
+                       when "01" => byte_en(1) := '1';
+                       when "10" => byte_en(2) := '1';
+                       when "11" => byte_en(3) := '1';
+                       when others => null;
+                       end case;
+               else
+                       byte_en := (others => '1');
+               end if;
        end if;
+       wb_reg_nxt.byte_en <= byte_en;
+       
+       -- if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then        -- ram read operation --alu_jmp = '0' and 
+               -- calc_mem_res <= data_ram_read;
+               -- if (wb_reg.hword = '1') then
+                       -- calc_mem_res <= (others => '0');
+                       -- if (wb_reg.address(1) = '1') then
+                               -- calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16);
+                       -- else
+                               -- calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0);
+                       -- end if;
+               -- end if;
+               -- if (wb_reg.byte_s = '1') then
+                       -- calc_mem_res <= (others => '0');
+                       -- case wb_reg.address(1 downto 0) is
+                               -- when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0);
+                               -- when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8);
+                               -- when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16);
+                               -- when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24);
+                               -- when others => null;
+                       -- end case;
+               -- end if;      
+       -- end if;
 
        --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
        jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
@@ -143,7 +172,7 @@ begin
 
 --     if ((alu_jmp and wb_reg.dmem_en) = '1') then
 --             jump_addr <= data_ram_read;
---     end if;
+--     end if; 
 
 end process;
 
@@ -159,59 +188,95 @@ end process;
 
 
 
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res)
-
-begin  
-       reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel)
+variable reg_we_v : std_logic;
+variable data_out : gp_register_t;
+begin
+    reg_we_v := (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
        reg_addr <= result_addr;
 
        data_addr <= (others => '0');
        dmem_we <= '0';
        
+       if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+               data_out := data_ram_read;
+       else
+               reg_we_v := reg_we_v and ext_anysel;
+               data_out := data_ram_read_ext;
+       end if;
+       
+       if wb_reg.byte_en(0) = '0' then
+               data_out(byte_t'range) := (others => '0');
+       end if;
+       if wb_reg.byte_en(1) = '0' then
+               data_out(2*byte_t'length-1 downto byte_t'length) := (others => '0');
+       end if;
+       if wb_reg.byte_en(2) = '0' then
+               data_out(3*byte_t'length-1 downto 2*byte_t'length) := (others => '0');
+       end if;
+       if wb_reg.byte_en(3) = '0' then
+               data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
+       end if;
+       
+       data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))); 
+       
        if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
                dmem_we <= wb_reg_nxt.dmem_write_en;
        end if;
        
-       regfile_val <= calc_mem_res;
-
-       if (wb_reg.address(31 downto 4) = EXT_UART_ADDR) then
-               regfile_val <= data_ram_read_ext;
-       end if;
+       regfile_val <= data_out;
+       
+       reg_we <= reg_we_v;
+       
 end process;
 
 
-addr_de_mult: process(wb_reg_nxt, ram_data, wb_reg,sel_nxt)
-
+addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_gpmp_out, ext_timer_out)
+variable wr_en, enable  : std_logic; -- these are all registered
+variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them
+variable addr : ext_addr_t;   -- for example the data memory, because it already has input registers
+variable addrid : ext_addrid_t;
+variable data : gp_register_t;
 begin
 
-  ext_uart.sel <='0';
-  ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
-  ext_uart.byte_en <= (others => '0');
-  ext_uart.data <= (others => '0');
-  ext_uart.addr <= (others => '0');
+ --if selecting enable is too slow, see alu_b
+  enable := wb_reg.dmem_en;
+  wr_en  := wb_reg.dmem_write_en;
+  byte_en := wb_reg.byte_en;
+  addr := wb_reg.address(gp_register_t'high downto BYTEADDR);
+  addrid := wb_reg.address(gp_register_t'high downto EXTWORDS);
+  data := wb_reg.data;
 
+  ext_uart.sel <='0';
   ext_7seg.sel <='0';
-  ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
-  ext_7seg.byte_en <= (others => '0');
-  ext_7seg.data <= (others => '0');
-  ext_7seg.addr <= (others => '0');
-  
   ext_timer.sel <='0';
-  ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
-  ext_timer.byte_en <= (others => '0');
-  ext_timer.data <= (others => '0');
-  ext_timer.addr <= (others => '0');
-
   ext_gpmp.sel <='0';
-  ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
-  ext_gpmp.byte_en <= (others => '0');
-  ext_gpmp.data <= (others => '0');
-  ext_gpmp.addr <= (others => '0');
+  
+  ext_uart.wr_en <= wr_en;
+  ext_7seg.wr_en <= wr_en;
+  ext_timer.wr_en <= wr_en;
+  ext_gpmp.wr_en <= wr_en;
+  
+  ext_uart.byte_en <= byte_en;
+  ext_7seg.byte_en <= byte_en;
+  ext_timer.byte_en <= byte_en;
+  ext_gpmp.byte_en <= byte_en;
+  
+  ext_uart.addr <= addr;
+  ext_7seg.addr <= addr;
+  ext_timer.addr <= addr;
+  ext_gpmp.addr <= addr;
+
+  ext_uart.data <= data;
+  ext_7seg.data <= data;
+  ext_timer.data <= data;
+  ext_gpmp.data <= data;
    -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
- case wb_reg_nxt.address(31 downto 4) is
---     when EXT_UART_ADDR => 
---             ext_uart.sel <='1';
+ case addrid is
+    when EXT_UART_ADDR => 
+       ext_uart.sel <= enable;
+               ext_anysel <= enable;
 --             ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
 --             ext_uart.data <= ram_data;
 --             ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
@@ -225,11 +290,12 @@ begin
 --                     end case;
 
        when EXT_7SEG_ADDR => 
-               ext_7seg.sel <='1';
-               ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
-               ext_7seg.data <= ram_data;
-               ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
-               ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
+               ext_7seg.sel <= enable;
+               ext_anysel <= enable;
+               -- ext_7seg.wr_en <= wb_regdmem_write_en;
+               -- ext_7seg.data <= ram_data;
+               -- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
+               -- ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
 
                
 --             case wb_reg_nxt.address(1 downto 0) is
@@ -241,33 +307,36 @@ begin
 --             end case;
                        
        when EXT_TIMER_ADDR => 
-               ext_timer.sel <='1';
-               ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
-               ext_timer.data <= ram_data;
-               ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
-               case wb_reg.address(1 downto 0) is
-                               when "00" => ext_timer.byte_en <= "0001";
-                               when "01" => ext_timer.byte_en <= "0010";
-                               when "10" => ext_timer.byte_en <= "0100";
-                               when "11" => ext_timer.byte_en <= "1000";
-                               when others => null;
-                       end case;
+               ext_timer.sel <= enable;
+               ext_anysel <= enable;
+               -- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
+               -- ext_timer.data <= ram_data;
+               -- ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+               -- case wb_reg.address(1 downto 0) is
+                               -- when "00" => ext_timer.byte_en <= "0001";
+                               -- when "01" => ext_timer.byte_en <= "0010";
+                               -- when "10" => ext_timer.byte_en <= "0100";
+                               -- when "11" => ext_timer.byte_en <= "1000";
+                               -- when others => null;
+                       -- end case;
        when EXT_GPMP_ADDR => 
-               ext_gpmp.sel <='1';
-               ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
-               ext_gpmp.data <= ram_data;
-               ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
-               case wb_reg.address(1 downto 0) is
-                               when "00" => ext_gpmp.byte_en <= "0001";
-                               when "01" => ext_gpmp.byte_en <= "0010";
-                               when "10" => ext_gpmp.byte_en <= "0100";
-                               when "11" => ext_gpmp.byte_en <= "1000";
-                               when others => null;
-                       end case;
+               ext_gpmp.sel <= enable;
+               ext_anysel <= enable;
+               -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
+               -- ext_gpmp.data <= ram_data;
+               -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+               -- case wb_reg.address(1 downto 0) is
+                               -- when "00" => ext_gpmp.byte_en <= "0001";
+                               -- when "01" => ext_gpmp.byte_en <= "0010";
+                               -- when "10" => ext_gpmp.byte_en <= "0100";
+                               -- when "11" => ext_gpmp.byte_en <= "1000";
+                               -- when others => null;
+                       -- end case;
        -- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert 
-       when others => null;
- end case;
-
+       when others => ext_anysel <= '0';
+       end case;
+       
+       data_ram_read_ext <= ext_uart_out or ext_gpmp_out or ext_timer_out;
 end process;
 
 end behav;

diff --git a/cpu/src/writeback_stage_b.vhd.bak b/cpu/src/writeback_stage_b.vhd.bak
deleted file mode 100644 (file)
index 2c449ba..0000000
--- a/cpu/src/writeback_stage_b.vhd.bak
+++ /dev/null
@@ -1,156 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-use work.common_pkg.all;
-use work.core_pkg.all;
-
-use work.mem_pkg.all;
-use work.extension_pkg.all;
-
-architecture behav of writeback_stage is
-
-signal data_ram_read : word_t;
-
-signal wb_reg, wb_reg_nxt : writeback_rec;
-signal ext_uart :  extmod_rec;
-
-
-
-begin
-
-
-       data_ram : r_w_ram
-               generic map (
-                       DATA_ADDR_WIDTH,
-                       WORD_WIDTH
-               )
-               
-               port map (
-                       clk,
-                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.dmem_write_en,
-                       ram_data,
-                       data_ram_read
-               );
-
-
-syn: process(clk, reset)
-
-begin
-
-       if (reset = RESET_VALUE) then
-               wb_reg.address <= (others => '0');
-               wb_reg.dmem_en <= '0';
-               wb_reg.dmem_write_en <= '0';
-               wb_reg.hword <= '0';
-               wb_reg.byte_s <= '0';
-       elsif rising_edge(clk) then
-               wb_reg <= wb_reg_nxt;
-       end if;
-       
-end process; 
-
---     type writeback_rec is record
---             address : in word_t;            --ureg 
---             dmem_en : in std_logic;         --ureg (jump addr in mem or in address)
---             dmem_write_en : in std_logic;   --ureg
---             hword_hl : in std_logic         --ureg
---     end record;
-
-
-
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
-
-begin
-       wb_reg_nxt.address <= address;
-       wb_reg_nxt.dmem_en <= dmem_en;
-       wb_reg_nxt.dmem_write_en <= dmem_write_en;
-       wb_reg_nxt.hword <= hword;
-       wb_reg_nxt.byte_s <= byte_s;
-
-       regfile_val <= result; --(others => '0');
-
-       if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then   -- ram read operation --alu_jmp = '0' and 
-               regfile_val <= data_ram_read;
-               if (wb_reg.hword = '1') then
-                       regfile_val <= (others => '0');
-                       if (wb_reg.address(1) = '1') then
-                               regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
-                       else
-                               regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
-                       end if;
-               end if;
-               if (wb_reg.byte_s = '1') then
-                       regfile_val <= (others => '0');
-                       case wb_reg.address(1 downto 0) is
-                               when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
-                               when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
-                               when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
-                               when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
-                               when others => null;
-                       end case;
-               end if; 
-       end if;
-
-       jump <= alu_jmp xor br_pred;
-       jump_addr <= result;
-       if ((alu_jmp and wb_reg.dmem_en) = '1') then
-               jump_addr <= data_ram_read;
-       end if;
-
-end process;
-
---                     result : in gp_register_t;      --reg  (alu result or jumpaddr)
---                     result_addr : in gp_addr_t;     --reg
---                     address : in word_t;            --ureg 
---                     alu_jmp : in std_logic;         --reg
---                     br_pred : in std_logic;         --reg
---                     write_en : in std_logic;        --reg  (register file)
---                     dmem_en : in std_logic;         --ureg (jump addr in mem or in result)
---                     dmem_write_en : in std_logic;   --ureg
---                     hword : in std_logic            --ureg
-
-
-
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
-
-begin  
-       reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
-       reg_addr <= result_addr;
-end process;
-
-
-addr_de_mult: process(address)
-
-begin
-
-  ext_uart.sel <='0';
-  ext_uart.wr_en <= '0';
-  ext_uart.byte_en <= (others => '0');
-  ext_uart.data <= (others => '0');
-  ext_uart.addr <= (others => '0');
- case wb_reg_nxt.address(wb_reg_nxt.address'high downto EXTWORDS) is
-       when EXT_UART_ADDR => 
-               ext_uart.sel <='1';
-               ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
-               ext_uart.data <= ram_data;
-               ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
-               case wb_reg.address(1 downto 0) is
-                               when "00" => ext_uart.byte_en <= "0001";
-                               when "01" => ext_uart.byte_en <= "0010";
-                               when "10" => ext_uart.byte_en <= "0100";
-                               when "11" => ext_uart.byte_en <= "1000";
-                               when others => null;
-                       end case;
-               
-
-
-       when others => null;
- end case;s
-
-end process;
-
-end behav;
-