2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
9 use work.extension_pkg.all;
11 architecture behav of writeback_stage is
13 signal data_ram_read : word_t;
15 signal wb_reg, wb_reg_nxt : writeback_rec;
16 signal ext_uart : extmod_rec;
31 wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
32 wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
33 wb_reg_nxt.dmem_write_en,
39 syn: process(clk, reset)
43 if (reset = RESET_VALUE) then
44 wb_reg.address <= (others => '0');
45 wb_reg.dmem_en <= '0';
46 wb_reg.dmem_write_en <= '0';
49 elsif rising_edge(clk) then
55 -- type writeback_rec is record
56 -- address : in word_t; --ureg
57 -- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
58 -- dmem_write_en : in std_logic; --ureg
59 -- hword_hl : in std_logic --ureg
64 shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
67 wb_reg_nxt.address <= address;
68 wb_reg_nxt.dmem_en <= dmem_en;
69 wb_reg_nxt.dmem_write_en <= dmem_write_en;
70 wb_reg_nxt.hword <= hword;
71 wb_reg_nxt.byte_s <= byte_s;
73 regfile_val <= result; --(others => '0');
75 if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
76 regfile_val <= data_ram_read;
77 if (wb_reg.hword = '1') then
78 regfile_val <= (others => '0');
79 if (wb_reg.address(1) = '1') then
80 regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
82 regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
85 if (wb_reg.byte_s = '1') then
86 regfile_val <= (others => '0');
87 case wb_reg.address(1 downto 0) is
88 when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
89 when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
90 when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
91 when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
97 jump <= alu_jmp xor br_pred;
99 if ((alu_jmp and wb_reg.dmem_en) = '1') then
100 jump_addr <= data_ram_read;
105 -- result : in gp_register_t; --reg (alu result or jumpaddr)
106 -- result_addr : in gp_addr_t; --reg
107 -- address : in word_t; --ureg
108 -- alu_jmp : in std_logic; --reg
109 -- br_pred : in std_logic; --reg
110 -- write_en : in std_logic; --reg (register file)
111 -- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
112 -- dmem_write_en : in std_logic; --ureg
113 -- hword : in std_logic --ureg
117 out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
120 reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
121 reg_addr <= result_addr;
125 addr_de_mult: process(address)
130 ext_uart.wr_en <= '0';
131 ext_uart.byte_en <= (others => '0');
132 ext_uart.data <= (others => '0');
133 ext_uart.addr <= (others => '0');
134 case wb_reg_nxt.address(wb_reg_nxt.address'high downto EXTWORDS) is
135 when EXT_UART_ADDR =>
137 ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
138 ext_uart.data <= ram_data;
139 ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
140 case wb_reg.address(1 downto 0) is
141 when "00" => ext_uart.byte_en <= "0001";
142 when "01" => ext_uart.byte_en <= "0010";
143 when "10" => ext_uart.byte_en <= "0100";
144 when "11" => ext_uart.byte_en <= "1000";